January 1994

13

Philips Semiconductors

Preliminary specification

Synchronization circuit with synchronized

vertical divider system for 60 Hz

TDA2579C

duration of output pulse HIGH

storage time

horizontal deflection

stage = 10

µs

27

29

31

µs

TC

temperature coefficient

K

influence of delay time on pulse width of

horizontal output signal

−

0.16

−µs/µs

controlled edge

−

positive

−

Sandcastle output signal (pin 17)

output voltage during:

burst key

9.8

10.4

−

V

horizontal blanking

4.1

4.5

4.9

V

vertical blanking

2.1

2.5

2.9

V

zero level output voltage

−

0.7

−

V

burst key pulse width

60 Hz

3.4

3.65

4

µs

horizontal blanking level

−

1

−

V

vertical blanking

note 9

phase position burst key time between

middle sync pulse at pin 5 and start burst

key pulse at pin 17

2.3

2.7

3.1

µs

phase position burst key time between start

sync pulse at pin 5 and end of burst key

pulse at pin 17

60 Hz

−−

9.1

µs

Coincidence detector, video transmitter identification circuit and time constant switching levels (see Fig.1)

detector output current

−

0.25

−

mA

voltage level for in sync condition

5.8

6.4

7

V

voltage level for noisy sync pulse

9

10.1

−

V

voltage level for noise only

note 10

−

0.3

−

V

switching level:

normal to fast

<3.2

3.5

3.8

V

mute output active and fast to normal

<1.0

1.2

1.4

V

field period counter

3 periods fast

<0.08

0.12

0.16

V

normal to fast mute output inactive

locking

>1.5

1.75

2

V

fast to normal

locking

>4.7

5

5.3

V

normal to slow

gated sync pulse

>7.4

7.8

8.2

V

Video transmitter identification output (pin 13)

output voltage active

−

0.15

0.32

V

sink current active

−−

5mA

output current inactive

sync 60 Hz

−−

1

µA

pnp emitter follower voltage

note 11

7.2

7.65

8.1

V

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT