PI6050D Data Sheet

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Recommended Operating Conditions

Table 3 lists the recommended operating conditions @ 25

Parameter

Symbol

Min

Typ

Max

Units

Power Supply

Vdd

4.5

5.0

5.5

V

Clock Input Voltage high level

(1)

3.1

3.3

3.5

V

Clock Input Voltage low level

(1)

0

0

0.8

V

Power Supply Current

IDD (sensor selected)

IDD (sensor not selected)

8

4

10

5

mA

mA

Reference Voltage

(2)

VREF

1.3

1.7

1.7

V

Clock Frequency

(3)

0.25

1.25

1.5

MHz

Pixel Rate

(4)

0.5

2.5

3.0

MHz

Integration Time (Line Scan Rate)

(5)

First Die

Subsequent Die

Tint

248

230

µs

µs / die

Clock Pulse Duty Cycle

(6)

50

%

Table 3. Recommended Operating Conditions @ 25

Notes:

1.

Applies to all clocks; GBST, SI and CLK. The CLK line having a capacitance of approximately 20 pF.

2.

The dark level is set by the voltage on VREF and is recommended to be set externally to a voltage of 1.7V

for optimal module operation.

3.

Although the device will operate with a pixel rate of less than 500 KHz, it is recommended that the device be

operated above 500 KHz to maintain performance characteristics. Operating below 500 KHz may result in

leakage current degradation.

4.

2 pixels are clocked out for every clock cycle.

5.

Tint is the integration time of a single sensor and is the time between two Start Pulses. The minimum

integration time is the time it takes to clock out 55 inactive pixels and 688 active pixels for the 1200 dpi mode,

or 55 inactive pixels and 344 active pixels for the 600 dpi mode, at a given frequency.

However, if several sensors are cascaded together in a module then the minimum integration time for the

1200 dpi mode is the time it takes to clock out 55 inactive pixels and 688 active pixels from the first sensor

and 688 pixels from each of all subsequent sensors, at a given frequency.

Similarly, for cascaded sensors in the 600 dpi mode, the minimum integration time is the time it takes to

clock out 55 inactive pixels and 344 active pixels from the first sensor and 344 pixels from each of all

subsequent sensors, at a given frequency.

6.

The clock duty cycle is defined as the ratio of the positive duration of the clock to its period.

Page 8 of 15, PI6050D_rev A, Revised 1-31-05