Figure 4

Item

Symbol

Min.

Typical

Max.

Units

Clock cycle time

to

0.20

4.0

µs

Clock pulse width

tw

50

ns

Clock duty cycle

25

75

%

Prohibit crossing time

tprh

0

ns

Data setup time

tds

20

ns

Data hold time

tdh

0

ns

Signal delay time

tdl

20

ns

Signal settling time

tsh

100

ns

Note1:

"Prohibit crossing of start pulse" is to indicate that the start pulse should not be active high

between any two consecutive clock pulse, specifically, between two consecutive low going clock

pulses. See the timing diagram. All falling clock edges under a active high start pulse loads the

internal shift register, therefore the start pulse must be active over only one falling clock edge.

High start pulse over all rising clock edge is ignored by the shift register. One simple way to

ensure that the start pulse will not be actively high during two consecutive falling clock edge is to

generate the start pulse on a rising clock edge and terminate it on the following rising clock edge.

PAGE 9 OF 10 - PI227/228/229, 01-31-04

CP

SP

Vout

tds

to

tw

tprh

tdl

tdh

tsh

MODULE TIMING DIAGRAM