AMIS-710409-A4: 400dpi CIS Module

Data Sheet

10.0 Switching Characteristics (25

Figure 4: Module Timing Diagram

The switching characteristics (at 25°C) for the I/O clocks are shown in Figure 4. For the timing symbol definitions, see Table 6.

Note: Only one video output is shown because all four videos have identical electrical characteristics. The only physical difference

between them is in Section 4 output, VOUT4. Section 4 has only six sensor chips, hence its active scan is shorter by 128 pixels.

Table 6: Timing Symbol’s Definition and Timing Values

Item

Symbol

Min.

Typ.

Max.

Units

Clock cycle time

to

0.20

4.0

µs

Clock pulse width

tw

50

ns

Clock duty cycle

25

75

%

Prohibit crossing time of SP

(1)

tprh

0

ns

Data setup time

tds

20

ns

Data hold time

tdh

0

ns

Signal delay time

tdl

20

ns

Signal settling time

tsh

100

ns

Note:

(1)

"Prohibit crossing of start pulse" is to indicate that the start pulse should not be active high between any two consecutive high going clock pulses or two

consecutive low going clock pulses (see Figure 4). Only one high going clock under the active high start pulse initiates the internal shift register and it must not be

active over two high going clocks. All low going clock pulses will not initiate the shift register. To ensure that the start pulse will not be actively high during two

consecutive high going clocks, the circuit should be designed to keep the start pulse active only for one high going clock cycle.

6

AMI Semiconductor – July 06, M-20594-001

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