Data Sheet

9.0 Reset Level and Video Sampling Time

Figure 3: Video Pixel Definition

Figure 3 graphically shows the video signal waveform and defines the single video pixel structure. The signal output waveform is shown

relative to the input clock waveform, as well as the symbols and terminologies used to define the performance specifications. Figure 3

explains the terminology used to characterize the dark signal levels and the recommended video pixel sampling times.

Note 6, under Table 7, specifies the dark level (DL). This is the level seen during the dark read out; for example, either the module sits

on a black target or the light source is turned off. It is measured from ground or 0V. The reset level is a reference level for the reset

switch, which is not necessarily on ground because after the reset occurs, the signal is passed through an amplifier. The difference

between the dark level and the reset level is called the pedestal (PED). In most cases, the offset control of the amplifier is used to

adjust the dark level to 0V or ground. Hence, the reset level will sit below ground.

The video pixels demonstrated in this graph emanate from an ideal CIS module with a phototransistor imaging structure. The video

output at high speeds, such as 5.0MHz, does not instantly rise to its final value, although given enough time; it would asymptotically

approach its steady state value. But, at high speeds it is impractical to wait for the final stable value. Accordingly, as Figure 3 indicates,

the output signal continues to rise towards its steady state value. Consistent with the forgoing comments, under Table 7, instead of the

conventional signal sampling time, tst is defined to substitute the conventional settling time definition. This definition is used because

the output signal continues to rise asymptotically to the final stable value but not within a practical time in high speed applications. This

is true even when the video rises to its peak value, Vp, defined in the algorithm used in the measurements described by the following

equation:

MTF={[Vp(n)+Vp(n+1)]/2-[Vp(n+2)+Vp(n+3)]/2}/{[Vp(n)+Vp(n+1)]/2+[Vp(n+2)+Vp(n+3)]/2}

Where n is 1, 2, .....1728

5

AMI Semiconductor – Aug. 06, M-20608-001

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