February 1991

7

Philips Semiconductors

Product specification

Stereo high performance 16-bit DAC

TDA1541A

Notes to the characteristics

1. To ensure no performance losses, permitted output voltage compliance is

±25 mV maximum.

TDA1541A/N2

bit 1-16

TDA1541A/N2/R1

bit 1-16

TDA1541A/N2/S1

bit 1-7

bit 8-15

bit 16

THD

total harmonic distortion

including noise

at 0 dB;

note 3, Fig. 3, 4

−

−

−95

0.0018

−90

0.0032

dB

%

THD

total harmonic distortion

including noise

at

−60 dB;

note 3, Fig. 3, 4

−

−

−42

0.79

−

−

dB

%

settling time

±1 LSB

−

0.5

−µs

α

channel separation

90

98

−

dB

unbalance between outputs

note 4

−

< 0.1

0.3

dB

time delay between outputs

−−

0.2

µs

SSVR

supply voltage ripple rejection

note 4

−−76

−

dB

SSVR

supply voltage ripple rejection

note 4

−−84

−

dB

SSVR

supply voltage ripple rejection

note 4

−−58

−

dB

S/N

signal-to-noise ratio

at bipolar zero

−

110

−

dB

S/N

signal-to-noise ratio

at full scale

98

104

−

dB

Timing (Fig. 5 and 6)

rise time

−−

32

ns

fall time

−−

32

ns

bit clock cycle time

156

−−

ns

bit clock HIGH time

46

−−

ns

bit clock LOW time

46

−−

ns

bit clock fall time to latch enable

rise time

0

−−

ns

bit clock rise time to latch enable

fall time

0

−−

ns

data set-up time

32

−−

ns

data hold time to bit clock

0

−−

ns

word select hold time

0

−−

ns

word select set-up time

32

−−

ns

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT