SN54LVTH574, SN74LVTH574

3.3V ABT OCTAL EDGETRIGGERED DTYPE FLIPFLOPS

WITH 3STATE OUTPUTS

SCBS688G − MAY 1997 − REVISED SEPTEMBER 2003

2

POST OFFICE BOX 655303

description/ordering information (continued)

The eight flip-flops of the ’LVTH574 devices are edge-triggered D-type flip-flops. On the positive transition of

the clock (CLK) input, the Q outputs are set to the logic levels set up at the data (D) inputs.

A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high

or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive

the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus

lines without need for interface or pullup components.

OE does not affect the internal operations of the flip-flops. Old data can be retained or new data can be entered

while the outputs are in the high-impedance state.

resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. Use of pullup

or pulldown resistors with the bus-hold circuitry is not recommended.

disables the outputs, preventing damaging current backflow through the devices when they are powered down.

The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down,

which prevents driver conflict.

terminal assignments

1234

A

1D

OE

VCC

1Q

B

3D

3Q

2D

2Q

C

5D

4D

5Q

4Q

D

7D

7Q

6D

6Q

E

GND

8D

CLK

8Q

FUNCTION TABLE

(each flip-flop)

INPUTS

OUTPUT

OE

CLK

D

OUTPUT

Q

L

↑

H

H

L

↑

LL

L

H or L

X

Q0

H

X

X

Z

SN74LVTH574 . . . GQN OR ZQN PACKAGE

(TOP VIEW)

1

234

A

B

C

D

E