PLL620-80

Low Phase Noise XO (9.5-65MHz Output)

47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991

www.phaselink.com Rev 11/09/04 Page 1

FEATURES

• 19MHz to 65MHz crystal input.

• Output range: 9.5MHz – 65MHz

• Selectable OE Logic (enable high or enable low).

• Available outputs: PECL, LVDS, or CMOS (High

Drive (30mA) or Standard Drive (10mA) output).

• Supports 2.5V or 3.3V Power Supply.

• Available in die form.

DESCRIPTION

The PLL620-80 is a XO IC specifically designed to

19MHz and 65MHz. The selectable divide by two

feature extends the operation range from 9.5MHz to

65MHz. It requires very low current into the crystal

resulting in better overall stability. The OE logic

feature allows selection of enable high or enable low.

Furthermore, it provides selectable CMOS, PECL or

LVDS outputs.

DIE SPECIFICATIONS

Name

Value

Size

62 x 65 mil

Reverse side

GND

Pad dimensions

80 micron x 80 micron

Thickness

10 mil

BLOCK DIAGRAM

DIE CONFIGURATION

OUTPUT SELECTION AND ENABLE

OUT_SEL1*

(Pad 18)

OUT_SEL0*

(Pad 25)

Selected Output*

0

0

High Drive CMOS

0

1

Standard CMOS

1

0

LVDS

1

1

PECL (default)

OE_SELECT

(Pad 9)

OE_CTRL

(Pad 30)

State

0

Tri-state

0

1 (Default)

Output enabled

0 (Default)

Output enabled

1 (Default)

1

Tri-state

Pads #9, #18 & #25: Bond to GND to set to “0”,

No connection results to “default” setting

through internal pull-up.

OE_CTRL: Logical states defined by PECL levels if OE_SELECT is “1”

Logical states defined by CMOS levels if OE_SELECT is “0”

OUTPUT FREQUENCY SELECTOR

S2

Output

0

Input/2

1(Default)*

Input

*Internally set to ‘Default’ through 60K pull-up resistor

18

19

20

21

23

25

7

13

10

26

29

31

Y

X

(0,0)

(1550,1475)

65 mil

24

22

17

16

15

14

12

11

9

8

6

1

2

3

4

5

27

28

30

OE_SEL^

PECL

LVDS

VDDBUF

VDDBUF

PECLB

LVDSB

CMOS

GNDBUF

XIN

XOUT

N/C

OE

CTRL

S2^

N/C

Die ID:

A2020-20B

C502A

XIN

XOUT

OE

Q

PLL620-80

Q

Oscillator

Amplifier

S2