Philips Semiconductors

Preliminary specification

SC28L194

Quad UART for 3.3V and 5V supply voltage

1998 Sep 21

39

AC ELECTRICAL SPECIFICATIONS FOR COMMERCIAL AND INDUSTRIAL (3.3V) (continued)

SYMBOL

FIG #

PARAMETER

LIMITS

UNIT

SYMBOL

FIG. #

PARAMETER

MIN.

TYP.

MAX.

UNIT

Sclk Timing

15

10

ns

15

10

ns

Sclk frequency

0.1

20

MHz

Sclk rise and fall time (0.8 to 2.0 Volts)

5

ns

X1/X2 Communication Crystal Clock

X1 clock frequency

1

3.6864

4.0

MHz

X1 L / H

X1 Low / High time

80

135

ns

T/RFx1

X1 Rise and Fall time

10

ns

Counter/Timer Baud Rate Clock (External Clock Input)

Clock frequency

0

8

MHz

TC/TLH

C/T high and low time

20

15

ns

TC/TO

Delay C/T clock external to output pin

48

110

ns

DACKN Timing

DACK low from Sclk C4 rising edge

18

30

ns

DACK high from CEN high (Async)

18

30

ns

DACK high from C4 end rising edge (Sync)

20

30

ns

I/O Port External Clock

GPI to Rx/Tx clock out

50

80

ns

RxD setup to I/OP rising edge 1X mode

20

2

ns

I/OP falling edge to TxD out 1X mode

32

70

ns

GPO valid after write to GPOR

100

ns

NOTES:

1. Timing is illustrated and referenced with respect to W-RN and CEN inputs. Internal read and write activities are controlled by the Sclk as it

generates the several “C” timing as shown in the timing diagrams.

2. The minimum time before the rising edge of the next C2 time to stop the next bus cycle. CEN must return high after midpoint of C4 time and

before the C2 time of the next cycle.

3. Delay is from cEN high in Async mode to IRQN inactive, from end of C4 to IRQN inactive in Sync mode.

4. The minimum frequency values are not tested, but are guaranteed by design.

5. 1MHz specification is for crystal operation.