Slave-to-Master

A

read-data time slot begins like a write-one time slot. The

voltage on the data line must remain below VILMAX until

the read low time tRL is expired. During the tRL window,

when responding with a 0, the DS1990A starts pulling

the data line low; its internal timing generator determines

when this pulldown ends and the voltage starts rising

again. When responding with a 1, the DS1990A does not

hold the data line low at all, and the voltage starts rising

as soon as tRL is over.

The sum of tRL + δ (rise time) on one side and the internal

timing generator of the DS1990A on the other side define

the master sampling window (tMSRMIN to tMSRMAX) in

which the master must perform a read from the data line.

For most reliable communication, tRL should be as short

as permissible and the master should read close to but

no later than tMSRMAX. After reading from the data line,

the master must wait until tSLOT is expired. This guaran-

tees sufficient recovery time tREC for the DS1990A to get

ready for the next time slot.

PACKAGE TYPE

PACKAGE CODE

OUTLINE NO.

F3 iButton

IB#3NB

21-0252

F5 iButton

IB#5NB

21-0266

www.analog.com

Analog Devices │ 9

DS1990A

Serial Number iButton

Package Information

For the latest package outline information and land patterns (footprints), go to

www.maximintegrated.com/packages. Note that a “+”,

“#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing

pertains to the package regardless of RoHS status.