SC68C198 datasheet(21/49 Pages) PHILIPS

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Philips Semiconductors

Product specification

SC26C198 SC68C198

SC26L198 SC68L198

Octal UART with TTL compatibility at 3.3V

and 5V supply voltages

1995 May 1

356

Table 9. Command Register Code

Commands x’12, x13, x’14, x’15, x’1f (marked with*) are global and exist only in channel A’s register space.

Channel Command

Code

Channel

Command

Channel Command

Code

Channel

Command

CR[7:3]

Description

CR[7:3]

Description

00000

NOP

10000

Transmit Xon

00001

Reserved

10001

Transmit Xoff

00010

Reset Receiver

10010

Gang Write Xon Character Registers *

00011

Reset Transmitter

10011

Gang Write Xoff Character Registers *

00100

Reset Error Status

10100

Gang Load Xon Character Registers DC1 *

00101

Reset Break Change Interrupt

10101

Gang Load Xoff Character Registers DC3 *

00110

Begin Transmit Break

10110

Xoff Resume Command

00111

End Transmit Break

10111

Host Xoff Command

01000

Assert RTSN (I/O2 or I/O1)

11000

Cancel Transmit X Char command

01001

Negate RTSN (I/O2 or I/O1)

11001

Reserved

01010

Set time–out mode on

11010

Reserved

01011

Reserved

11011

Reset Address Recognition Status

01100

Set time–out mode off

11100

Reserved

01101

Block Error Status configure

11101

Reserved

01110

Reserved

11110

Reset All UART channel registers

01111

Reserved

11111

Reset Device *

Table 10. SR – Channel Status Register

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Received

Break

Framing Error

Parity

Error

Overrun Error

TxEMT

TxRDY

RxFULL

RxRDY

0 – No

1 – Yes

0 – No

1 – Yes

0 – No

1 – Yes

0 – No

1 – Yes

0 – No

1 – Yes

0 – No

1 – Yes

0 – No

1 – Yes

0 – No

1 – Yes

SR[7] – Received Break

This bit indicates that an all zero character of the programmed

length has been received without a stop bit. Only a single FIFO

position is occupied when a break is received; further entries to the

FIFO are inhibited until the RxD line returns to the marking state for

at least one half bit time (two successive edges of the internal or

external 1x clock). When this bit is set, the change in break bit in

the ISR (ISR[2]) is set. ISR[2] is also set when the end of the break

condition, as defined above, is detected. The break detect circuitry

is capable of detecting breaks that originate in the middle of a

received character. However, if a break begins in the middle of a

character, it must last until the end of the next character in order for

it to be detected.

SR[6] – Framing Error (FE)

This bit, when set, indicates that a stop bit was not detected when

the corresponding data character in the FIFO was received. The

stop bit check is made in the middle of the first stop bit position.

SR[5] – Parity Error (PE)

This bit is set when the ’with parity’ or ’force parity’ mode is

programmed and the corresponding character in the FIFO was

received with incorrect parity. In the special ’wake up mode’, the

parity error bit stores the received A/D bit.

SR[4] – Overrun Error (OE)

This bit, when set, indicates that one or more characters in the

received data stream have been lost. It is set upon receipt of a new

character when the RxFIFO is full and a character is already in the

receive shift register waiting for an empty FIFO position. When this

occurs, the character in the receive shift register (and its break

detect, parity error and framing error status, if any) is lost. This bit is

cleared by a reset error status command.

SR[3] – Transmitter Empty (TxEMT)

This bit is set when the transmitter underruns, i.e., both the TxFIFO

and the transmit shift register are empty.

It is set after transmission of the last stop bit of a character, if no

character is in the TxFIFO awaiting transmission. It is reset when

the TxFIFO is loaded by the CPU, or when the transmitter is

disabled.

SR[2] – Transmitter Ready (TxRDY)

This bit, when set, indicates that the TxFIFO is ready to be loaded

with a character. This bit is cleared when the TxFIFO is loaded by

the CPU and is set when the last character is transferred to the

transmit shift register. TxRDY is reset when the transmitter is

disabled and is set when the transmitter is first enabled, e.g.,

characters loaded in the TxFIFO while the transmitter is disabled will

not be transmitted.

SR[1] – RxFIFO Full (RxFULL)

This bit is set when a character is transferred from the receive shift

become full, i.e., all sixteen RxFIFO positions are occupied. It is

reset when the CPU reads the RxFIFO and that read leaves one

empty byte position. If a character is waiting in the receive shift

second read of the RxFIFO since the waiting character is

immediately loaded to the RxFIFO.

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