SAB9079 datasheet(18/48 Pages) PHILIPS

18 / 48 page

2000 Jan 13

Philips Semiconductors

Preliminary speciﬁcation

Multistandard Picture-In-Picture (PIP)

controller

SAB9079HS

SNonInt

This bit indicates the internal interface status of the sub

channel. A logic 0 indicates that the channel is in

interlaced mode, a logic 1 indicates that the channel is

non-interlaced.

Mask ID

This bit gives the version number of the chip. A logic 0

indicates that a SAB9079N1 is used, a logic 1 indicates

that a SAB9079N2 is used.

RepChano

These bits indicate the present picture number, counting

from 0, where replay acquisition is writing.

I2C-BUS DISPLAY SETTING REGISTERS

MPIPON and SPIPON

If MPIPON is set to logic 1 (see Table 10) the main PIP is

on. If it is set to logic 0 the main PIP is off. If SPIPON is set

to logic 1 the sub PIPs are on, in accordance with the

scheme of the PIPG bits (see Section “Positioning and

sizing of PIPs”). If SPIPON is set to logic 0 all the sub PIPs

are off. This can also be achieved by setting all PIPG bits

to zero.

MFreeze and SFreeze

MFreeze and SFreeze control the writing of data to the

VDRAM. If set to logic 0 the writing to the VDRAM is

disabled after the next VSYNC. If set to logic 1 the writing

is enabled after the next VSYNC.

I2CHold

The I2C-bus hold bit is set to logic 0 (default). This means

that all I2C-bus data is directly clocked into the internal

registers. A part of the I2C-bus data will be clocked in on

the next VSYNC (e.g. the reduction factors and the display

positioning). If the I2CHold bit is logic 1 that part of the

I2C-bus will not be clocked in on the next VSYNC. To make

the data available the I2CHold bit should be set to logic 0

again. This function is useful when much data has to be

sent and a screen update is not allowed when sending this

data. A list of I2C-bus registers which are clocked in on a

VSYNC is given below:

• MPIPON and SPIPON

• MFreeze, SFreeze and FillSet

• DNonInt, MNonInt and SNonInt

• PRIO

• BGHfp, BGVfp, MDHfp, MDVfp, SDHfp and SDVfp

• MHPic, MVPic, SHPic, SVPic, SHDis and SVDis

• PIPGc,r

• MHRed, MVRed, SHRed, SVRed, MLSel,

SLSel and SBSel

• OSDHfp, OSDVfp, OSDHDis and OSDVDis.

FillSet and FillOff

The FillSet bit sets the colour of all sub PIPs immediately

to a 30% grey value if is set to logic 1. If FillSet is set to

logic 0 then the 30% grey PIPs stay until the data in the

VDRAM is updated (unfrozen). This bit should be used in

the event that a new PIP mode is made in which the

VDRAM data becomes invalid. FillOff works the opposite

to FillSet. If this bit is set all the VDRAM data is made

visible in the PIPs and no PIP has a grey content. This bit

is generally not used.

MiS

If the MiS bit is set to logic 0 the main and sub channels

have their own independent memory spaces. If set to

logic 1 the main and sub channels share the same

memory space, this is only valid if the main and sub

channels have the same reduction factors.

YUVFilter

These bits control the vertical filtering of 1 : 1 for both the

Y* and UV channels independently. Several display filter

modes can be set with these bits. An overview is given in

Table 9. The Y filter should not be used in vertical 1

⁄1

modes.

Table 9

Display ﬁlter modes

CTE and LTE

Colour Transient Enhancement (CTE) can be set on or off.

Luminance Transient Enhancement (LTE) is controllable

via a scale, setting the scale value to 0H means that LTE

is off.

MODE

YUV FILTER

No ﬁlter

00H

UV 1 : 1 vertical ﬁlter

01H

Y1:1 vertical ﬁlter

10H

YUV1:1 vertical ﬁlter

11H

SAB9079 датащи(PDF) 18 Page - NXP Semiconductors

SAB9079 датащи(HTML) 18 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48

датащи скачать

ссылки URL