SAA5290ZP datasheet(13/33 Pages) PHILIPS

13 / 33 page

February 1995

Philips Semiconductors

Preliminary speciﬁcation

One page Economy Teletext/TV

microcontroller

SAA5290

FUNCTIONAL DESCRIPTION

Introduction

The SAA5290 is an integrated teletext decoder and

microcontroller. The teletext decoder is derived from the

SAA5254 single page teletext decoder IC, with a number

of enhancements to increase its suitability for on-screen

display applications. The microcontroller is a derivative of

the industry standard 80C51 microcontroller. A block

diagram of the SAA5290 is given in Fig.1.

Microcontroller

The functionality of the microcontroller used on the

SAA5290 is described here with reference to the industry

standard 80C51 microcontroller. A full description of its

functionality can be found in the handbook

80C51-based

8-bit microcontrollers IC20. Using the 80C51 as a

reference, the changes made for the SAA5290 fall into two

categories, features not supported by the SAA5290 and

features found on the SAA5290 but not supported by the

80C51.

80C51 features not supported by the SAA5290

INTERRUPT PRIORITY

The IP SFR is not implemented and all interrupts are

treated with the same priority level. The SAA5290 retains

the normal prioritization of interrupts within a level.

Table 6

Interrupts and their vector addresses

EVENT

PROGRAM MEMORY ADDRESS

Reset

000H

External INT0

003H

Timer 0

00BH

External INT1

013H

Timer 1

01BH

I2C-bus

053H

OFF-CHIP MEMORY

The SAA5290 does not support the use of off-chip

program memory or off-chip data memory. This means

that the SAA5290 does not have any of EA, RD, WR, ALE

or PSEN pins. The 4 MOVX instructions which move data

to and from external RAM should not be used.

IDLE AND POWER-DOWN MODES

Idle and power-down modes are not supported by the

SAA5290. As a consequence, the respective bits in PCON

are not available.

UART FUNCTION

The 80C51 UART is not available in the SAA5290. As a

consequence the SCON and SBUF SFRs are removed

and the ES bit in the IE SFR is unavailable.

Additional features for the SAA5290

The following features are provided by the SAA5290 in

addition to the standard 80C51 features.

INTERRUPTS

The external INT1 interrupt is modified to generate an

interrupt on both the rising and falling edges of the INT1

pin, when EX1 bit is set. This facility allows for software

pulse width measurement for handling of a remote control.

BIT LEVEL I2C-BUS INTERFACE

The bit-level serial I/O supports the I2C-bus. P1.6/SCL and

P1.7/SDA are the serial I/O pins. These two pins meet the

I2C-bus specification concerning the input levels and

output drive capability. Consequently, these pins have an

open-drain output configuration. All the four following

modes of the I2C-bus are supported.

• Master transmitter

• Master receiver

• Slave transmitter

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