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SAA5281ZP датащи(PDF) 4 Page - NXP Semiconductors |
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SAA5281ZP датащи(HTML) 4 Page - NXP Semiconductors |
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4 / 48 page ![]() 1996 Nov 04 4 Philips Semiconductors Preliminary specification Integrated Video input processor and Teletext decoder (IVT1.8*) SAA5281 PINNING SYMBOL PIN DESCRIPTION SOT240-1 SOT247-1 SOT319-2 VDD1 1 52 11 +5 V supply 1 OSCOUT 2 1 13 27 MHz crystal oscillator output OSCIN 3 2 14 27 MHz crystal oscillator input OSCGND 4 3 15 0 V crystal oscillator ground VSS1 5 4 and 5 16 0 V ground REF+ 6 6 18 positive reference voltage for ADC; this pin should be connected to ground via a 100 nF capacitor BLACK 7 8 19 video black level storage input/output; this pin should be connected to ground via a 100 nF capacitor CVBS 8 9 20 composite video input; a positive-going 1 V (peak-to-peak) input is required, connected via a 100 nF capacitor IREF 9 10 21 reference current input, connected to ground via a 27 k Ω resistor VDD2 10 11 22 +5 V supply 2 POL 11 12 23 STTV/LFB/FFB polarity selection input STTV/LFB 12 13 24 sync to TV output line flyback input; function controlled by an internal register bit (scan sync mode) VCR/FFB 13 14 27 PLL time constant switch/field input; function controlled by an internal register bit (scan sync mode) VSS2 14 15 28 0 V ground; connected to VSS1 for normal operation R 15 16 30 dot rate character output of the RED colour information G 16 17 32 dot rate character output of the GREEN colour information B 17 18 33 dot rate character output of the BLUE colour information RGBREF 18 19 34 input DC voltage to define the output high level on the RGB pins BLAN 19 20 35 dot rate fast blanking output COR 20 21 36 programmable output to provide contrast reduction of the TV picture for mixed text and picture displays or when viewing newsflash/subtitle pages; open-drain output ODD/EVEN (or DV) 21 22 37 in ODD/EVEN mode a 25 Hz output synchronized with the CVBS input field sync pulses to produce a non-interlaced display by adjustment of the vertical deflection currents; in DV mode a VPT data valid signal is used to indicate reception of error-free VPS or 8/30 format 2 data Y 22 23 38 dot rate character output of teletext foreground colour information; open-drain output SCL 23 24 39 serial clock input for I2C-bus; it can still be driven HIGH during power-down of the device SDA 24 25 40 serial data port for the I2C-bus, open-drain output; it can still be driven HIGH during power-down of the device VSS3 25 26 44 0 V ground |
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