SP7655ERLSLASHTR datasheet(9/16 Pages) SIPEX

9 / 16 page

Rev E: 3/2/07

SP7655 Wide Input Voltage Range 8A, 300kHz, Buck Regulator

APPLICATIONS INFORMATION

The capacitor type suitable for the output capac-

itors can also be used for the input capacitors.

However, exercise additional caution when tanta-

lum capacitors are used. Tantalum capacitors are

known for catastrophic failure when exposed to

surge current, and input capacitors are prone to

such surge current when power supplies are con-

nected “live” to low impedance power sources.

Although tantalum capacitors have been success-

fully employed at the input, it is generally not

recommended.

Loop Compensation Design

The open loop gain of the whole system can be

divided into the gain of the error amplifier,

PWM modulator, buck converter output stage,

and feedback resistor divider. In order to cross

over at the desired frequency cut-off (FCO), the

gain of the error amplifier compensates for the

attenuation caused by the rest of the loop at this

frequency. The goal of loop compensation is to

manipulate loop frequency response such that

its cross-over gain at 0db, results in a slope of -

20db/dec.

The first step of compensation design is to pick

the loop crossover frequency. High crossover

frequency is desirable for fast transient response,

but often jeopardizes the power supply stability.

Crossover frequency should be higher than the

ESR zero but less than 1/5 of the switching

frequency or 60kHz. The ESR zero is contrib-

uted by the ESR associated with the output

capacitors and can be determined by:

ƒZ(ESR)=

2 C OUT R ESR

The next step is to calculate the complex conju-

gate poles contributed by the LC output filter,

ƒP(LC)=

L C OUT

When the output capacitors are of a Ceramic

Type, the SP7655 Evaluation Board requires a

Type III compensation circuit to give a phase

boost of 180° in order to counteract the effects of

an underdamped resonance of the output filter at

the double pole frequency.

SP7655 Voltage Mode Control Loop with Loop Dynamic

(SRz2Cz2+1)(SR1Cz3+1)

(SRESRCOUT+ 1)

[S^2LCOUT+S(RESR+RDC) COUT+1]

VIN

SR1Cz2(SRz3Cz3+1)(SRz2Cp1+1)

VRAMP_PP

VOUT

(Volts)

VREF

(Volts)

Notes: RESR= Output Capacitor Equivalent Series Resistance.

RDC= Output Inductor DC Resistance.

VRAMP_PP= SP6132 Internal RAMP Amplitude Peak to Peak Voltage.

Condition: Cz2 >> Cp1 & R1 >> Rz3

Output Load Resistance >> RESR& R DC

VREF

(R1 + R2)

VOUT

VFBK

(Volts)

Type III Voltage Loop

Compensation

GAMP(s) Gain Block

PWM Stage

GPWMGain

Block

Output Stage

GOUT(s) Gain

Block

Voltage Feedback

GFBKGain Block

Definitions:

RESR= Output Capacitor Equivalent Series Resistance

RDC= Output Inductor DC Resistance

RRAMP_PP= SP7655 internal RAMP Amplitude Peak to Peak Voltage

Conditions:

CZ2 >> Cp1 and R1 >> Rz3

Output Load Resistance >>

RESRand RDC

SP7655ERL/TR датащи(PDF) 9 Page - Sipex Corporation

SP7655ERL/TR датащи(HTML) 9 Page - Sipex Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

датащи скачать

ссылки URL