Nov 20-06 Rev J

SP6339-SP6341 Triple µPower Supervisory Circuit

© Copyright 2006 Sipex Corporation

7

Figure 1: functionality of the SP6339 and SP6341.

• V1 > Vth1, V2 > Vth2 , and V3 > Vth3 (all supplies over their corresponding thresh-

olds)----> RSTB is de-asserted after reset timeout period (Trp) & WDOB de-asserts

immediately without waiting for reset timeout period.

• MRIB goes to “LOW” to force “Reset” ----> RSTB is asserted immediately & WDOB is

not affected by MRIB and is not asserted.

• WDI keeps making transitions within watchdog timeout period (t<Twd) ----> neither

RSTB nor WDOB changes state.

• One of the supplies drops below its corresponding threshold (in this case V3) ---->

RSTB is asserted immediately & WDOB is asserted immediately too. Whenever V1, V2,

V3 are below their specified thresholds WDOB is asserted.

THEORY OF OPERATION

V1

V2

V3

Vth1

Vth2

Vth3=0.5V

MRIB

WDI

RSTB

Trp

Trp

T<Twd

T<Twd

T>Twd

T<Twd

WDOB