SP3220EB datasheet(12/21 Pages) SIPEX

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Date: 8/30/05

SP3220E/EB/EU High ESD RS-232 Driver/Receiver

Date: 8/22/05

SP3220E/EB/EU High ESD RS-232 Driver/Receiver

Phase 4

— V

DD transfer — The fourth phase of the clock

connects the negative terminal of C

2 to GND, and

transfers this positive generated voltage across C

to C

4, the VDD storage capacitor. This voltage is

regulated to +5.5V. At this voltage, the internal

oscillator is disabled. Simultaneous with the trans-

fer of the voltage to C

4, the positive side of capaci-

tor C

1 is switched to VCC and the negative side is

connected to GND, allowing the charge pump

cycle to begin again. The charge pump cycle will

continue as long as the operational conditions for

the internal oscillator are present.

In a no–load condition V+ and V– will be symmetri-

cal, since both V+ and V– are separately generated

from V

CC.

Older charge pump approaches that

generate V– from V+ will show a decrease in the

magnitude of V– compared to V+ due to the

inherent inefficiencies in the design.

CHARGE PUMP DESIGN GUIDELINES

The charge pump operates with 0.1µF ca-

pacitors for 3.3V operation. For other supply

voltages, see the table for required capacitor

values. Do not use values smaller than those

listed. Increasing the capacitor values (e.g.,

by doubling in value) reduces ripple on the

transmitter outputs and may slightly reduce

power consumption. C2, C3, and C4 may be

increased without changing C1’s value.

The charge pump oscillator typically operates

at greater than 250kHz allowing the pump to

run efficiently with small 0.1µF capacitors.

Efficient operation depends on rapidly charg-

ing and discharging C

1 and C2, therefore

capacitors should be mounted close to the IC

and have low ESR (equivalent series resis-

tance).

Low cost surface mount ceramic capacitors

(such as are widely used for power-supply

decoupling) are ideal for use on the charge

pump. However the charge pumps are de-

signed to be able to function properly with a

wide range of capacitor styles and values. If

polarizedcapacitorsareusedthepositiveand

negative terminals should be connected as

shown in the Typical Operating Circuit.

Voltage potential across any of the capacitors

will never exceed 2 x V

CC. Therefore capaci-

tors with working voltages as low as 6.3V

rating may be used with a 3.0V V

CC supply.

The reference terminal of the V+ capacitor

may be connected either to V

CC or ground, but

if connected to ground a minimum 10V work-

ing voltage is required. Higher working volt-

ages and/or capacitance values may be ad-

vised if operating at higher V

CC or to provide

greater stability as the capacitors age.

Under lightly loaded conditions the intelligent

pump oscillator maximizes efficiency by run-

ning only as needed to maintain V+ and V-.

Sinceinterfacetransceiversoftenspendmuch

of their time at idle, this power-efficient inno-

vation can greatly reduce total power con-

sumption. This improvement is made pos-

sible by the independent phase sequence of

the Sipex charge-pump design.

–

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