XRT86VL32IB datasheet(39/65 Pages) EXAR

39 / 65 page

XRT86VL32

REV. V1.2.0

DUAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION

V13

Microprocessor Interface—Chip Select Input:

The user must assert this active low signal in order to select the

Microprocessor Interface for READ and WRITE operations

between the Microprocessor and the XRT86VL32 on-chip reg-

isters and buffer/memory locations.

Microprocessor Interface—Read Strobe Input:

The exact behavior of this pin depends upon the type of Micro-

processor/Microcontroller the Framer has been configured to

operate in, as defined by the PTYPE[2:0] pins.

Intel-Asynchronous Mode - RD* - READ Strobe Input:

This input pin will function as the RD* (Active Low Read

Strobe) input signal from the Microprocessor. Once this active-

low signal is asserted, then the XRT86VL32 device will place

the contents of the addressed register (or buffer location) on

the

Microprocessor Interface Bi-directional data bus (D[7:0]).

When this signal is negated, then the Data Bus will be tri-

stated.

Motorola-Asynchronous (68K) Mode - DS* - Data Strobe:

This input pin will function as the DS* (Data Strobe) input sig-

nal.

Power PC 403 Mode - WE* - Write Enable Input:

This input pin will function as the WE* (Write Enable) input pin.

Anytime the Microprocessor Interface samples this active-low

input signal (along with CS* and WR/R/W*) also being asserted

(at a logic low level) upon the rising edge of PCLK, then the

Microprocessor Interface will (upon the very same rising edge

of PCLK) latch the

contents on the Bi-Directional Data Bus (D[7:0]) into the “tar-

get” on-chip register or buffer location within the XRT86VL32

device.

MICROPROCESSOR INTERFACE

SIGNAL NAME

BALL #TYPE

OUTPUT

DRIVE (MA)

DESCRIPTION

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