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MP1541 датащи(PDF) 6 Page - Monolithic Power Systems |
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MP1541 датащи(HTML) 6 Page - Monolithic Power Systems |
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6 / 8 page ![]() MP1541 – 1.3MHz BOOST CONVERTER MP1541 Rev.1.3 www.MonolithicPower.com 6 3/20/2006 MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2006 MPS. All Rights Reserved. Compensation The MP1541 uses an amplifier to compensate the feedback loop rather than a traditional transconductance amplifier like most current mode regulators. Frequency compensation is provided by an internal resistor and capacitor along with an external resistor. The system uses two poles and one zero to stabilize the control loop. The poles are fP1 set by the output capacitor and load resistance, and fP2 set by the internal compensation capacitor Cc, the gain of the error amplifier and the resistance seen looking out at the feedback node REQ. The zero fZ1 is set internally around 20kHz. These are determined by the equations: LOAD 1 P R 2 C 1 f × × π = () EQ 9 2 P R 10 9 . 7 2 1 f × × × π × = − kHz 20 f 1 Z = Where RLOAD is the load resistance and REQ is: ) 2 R 1 R ( ) 2 R 1 R ( 3 R REQ + × + = Where R1, R2, and R3 are seen in Figure 2. The DC loop gain is: 2 OUT FB LOAD IN VDC V V R V 500 A ∗ ∗ ∗ = There is also a right-half-plane zero (fRHPZ) that exists in all continuous mode (inductor current does not drop to zero on each cycle) step up converters. The frequency of the right half plane zero is: 2 OUT LOAD 2 IN RHPZ V L 2 R V f × × π × × = To stabilize the regulation control loop, the crossover frequency (the frequency where the loop gain drops to 0dB or a gain of 1, indicated as fC) should be at least one decade below the right-half-plane zero and should be at most 75kHz. fRHPZ is at its lowest frequency at maximum output load current (RLOAD is at a minimum) and minimum input voltage. For the MP1541 it is recommended that a 47kΩ to 100kΩ resistor be placed in series with the FB pin and the resistor divider as seen in Figure 2. For most applications this is all that is needed for stable operation. If greater phase margin is needed a series resistor and capacitor can be placed in parallel with the high-side resistor R1 as seen in Figure 2. The pole and zero set by the lead-lag compensation network are: ⎟ ⎟ ⎟ ⎟ ⎠ ⎞ ⎜ ⎜ ⎜ ⎜ ⎝ ⎛ + + + × × π × = 3 R 1 2 R 1 1 R 1 1 4 R 3 C 2 1 f 3 P () 4 R 1 R 3 C 2 1 f 2 Z + × × π × = LAYOUT CONSIDERATIONS High frequency switching regulators require very careful layout for stable operation and low noise. All components must be placed as close to the IC as possible. Keep the path between L1, D1, and C2 extremely short for minimal noise and ringing. C1 must be placed close to the IN pin for best decoupling. All feedback components must be kept close to the FB pin to prevent noise injection on the FB pin trace. The ground return of C1 and C2 should be tied close to the GND pin. See the MP1541 demo board layout for reference. |
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