XRT83VSH28IB datasheet(65/74 Pages) EXAR

65 / 74 page

PRELIMINARY

XRT83VSH28

REV. P1.0.0

8-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT

TABLE 35: MICROPROCESSOR REGISTER 0X81H, BIT DESCRIPTION

0X81H

NAME

FUNCTION

TYPE

RESET

VALUE

BIT #

Reserved

R/W

Reserved

R/W

Reserved

R/W

Reserved

R/W

Reserved

R/W

RXMUTE

Receive Output Mute: Writing a “1” to this bit, mutes receive

outputs at RPOS/RDATA and RNEG/LCV pins to a “0” state for

any channel that detects an RLOS condition.

NOTE: RCLK is not muted.

R/W

EXLOS

Extended LOS: Writing a “1” to this bit extends the number of

zeros at the receive input of each channel before RLOS is

declared to 4096 bits. Writing a “0” reverts to the normal mode

(32 bits for E1).

R/W

ICT

In-Circuit-Testing: Writing a “1” to this bit configures all the

output pins of the chip in high impedance mode for In-Circuit-

Testing. Setting the ICT bit to “1” is equivalent to connecting

the Hardware ICT pin 88 to ground.

R/W

TABLE 36: MICROPROCESSOR REGISTER 0X82H BIT DESCRIPTION

GLOBAL REGISTER (0X82H)

BIT

NAME

FUNCTION

Type

Default

Value

(HW reset)

TxONCNTL Transmit On Control

0 = Control of Transmitter is set ;

if Hardware mode, by TxON pin

if Host mode, by TxON bit

1 = Control of transmitter on, is determined by the individual chan-

nel TxOn bits

R/W

TERCNTL

Receive Termination Select Control

This bit sets the LIU to control the RxTSEL function with either the

individual channel register bit or the global hardware pin.

0 = Control of the receive termination is set to the register bits

1 = Control of the receive termination is set to the RxTSEL hard-

ware pin

R/W

D[5:0]

Reserved

These Register Bits are Not Used

R/W

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