XRT83SL38IB datasheet(32/88 Pages) EXAR

32 / 88 page

XRT83SL38

OCTAL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

REV. 1.0.2

The driver monitor circuit is used to detect transmit driver failure by monitoring the activities at TTIP and TRING

outputs. Driver failure may be caused by a short circuit in the primary transformer or system problems at the

transmit input. If the transmitter of a channel has no output for more than 128 clock cycles, the corresponding

DMO pin goes “High” and remains “High” until a valid transmit pulse is detected. In Host mode, the failure of

the transmit channel is reported in the corresponding interface bit. If the DMOIE bit is also enabled, any

transition on the DMO interface bit will generate an interrupt. The driver failure monitor is supported in both

Hardware and Host modes on a per channel basis.

TRANSMIT PULSE SHAPER & LINE BUILD OUT (LBO) CIRCUIT

The transmit pulse shaper circuit uses the high speed clock from the Master timing generator to control the

shape and width of the transmitted pulse. The internal high-speed timing generator eliminates the need for a

tightly controlled transmit clock (TCLK) duty cycle. With the jitter attenuator not in the transmit path, the

transmit output will generate no more than 0.025Unit Interval (UI) peak-to-peak jitter. In Hardware mode, the

state of the A[4:0]/EQC[4:0] pins determine the transmit pulse shape for all eight channels. In Host mode

transmit pulse shape can be controlled on a per channel basis using the interface bits EQC[4:0]. The chip

supports five fixed transmit pulse settings for T1 Short-haul applications plus a fully programmable waveform

generator for arbitrary transmit output pulse shapes (The arbitrary pulse generators are available for both T1

and E1). The choice of the transmit pulse shape and LBO under the control of the interface bits are

summarized in Table 5. For CSU LBO transmit pulse design information, refer to ANSI T1.403-1993 Network-

to-Customer Installation specification, Annex-E.

NOTE:

EQC[4:0] determine the T1/E1 operating mode of the XRT83SL38. When EQC4 = “1” and EQC3 = “1”, the

XRT83SL38 is in the E1 mode, otherwise it is in the T1/J1 mode. For details on how to enable the E1 arbitrary

mode, see global register 0xC0h.

TABLE 5: RECEIVE EQUALIZER CONTROL AND TRANSMIT LINE BUILD-OUT SETTINGS

EQC4

EQC3

EQC2

EQC1

EQC0

E1/T1 MODE & RECEIVE

SENSITIVITY

TRANSMIT LBO

CABLE

CODING

T1 Short Haul/15dB

0-133 ft./ 0.6dB

100

Ω/ TP

B8ZS

T1 Short Haul/15dB

133-266 ft./ 1.2dB

100

Ω/ TP

B8ZS

T1 Short Haul/15dB

266-399 ft./ 1.8dB

100

Ω/ TP

B8ZS

T1 Short Haul/15dB

399-533 ft./ 2.4dB

100

Ω/ TP

B8ZS

T1 Short Haul/15dB

533-655 ft./ 3.0dB

100

Ω/ TP

B8ZS

T1 Short Haul/15dB

Arbitrary Pulse

100

Ω/ TP

B8ZS

T1 Gain Mode/29dB

0-133 ft./ 0.6dB

100

Ω/ TP

B8ZS

T1 Gain Mode/29dB

133-266 ft./ 1.2dB

100

Ω/ TP

B8ZS

T1 Gain Mode/29dB

266-399 ft./ 1.8dB

100

Ω/ TP

B8ZS

T1 Gain Mode/29dB

399-533 ft./ 2.4dB

100

Ω/ TP

B8ZS

T1 Gain Mode/29dB

533-655 ft./ 3.0dB

100

Ω/ TP

B8ZS

T1 Gain Mode/29dB

Arbitrary Pulse

100

Ω/ TP

B8ZS

E1 Short Haul

ITU G.703/Arbitrary

Ω Coax

HDB3

E1 Short Haul

ITU G.703/Arbitrary

120

Ω TP

HDB3

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