MPC8250 datasheet(20/60 Pages) FREESCALE

20 / 60 page

MPC8250 Hardware Specifications, Rev. 1

Freescale Semiconductor

Clock Configuration Modes

NOTE

The UPM machine outputs change on the internal tick determined by the

memory controller programming; the AC specifications are relative to the

internal tick. Note that SDRAM and GPCM machine outputs change on

CLKin’s rising edge.

Clock Configuration Modes

The MPC8250 has three clocking modes: local, PCI host, and PCI agent. The clocking mode is set

according to three input pins—PCI_MODE, PCI_CFG[0], PCI_MODCK—as shown in Table 12.

In each clocking mode, the configuration of bus, core, PCI, and CPM frequencies is determined by seven

bits during the power-up reset—three hardware configuration pins (MODCK[1–3]) and four bits from

hardware configuration word[28–31] (MODCK_H). Both the PLLs and the dividers are set according to

the selected MPC8250 clock operation mode as described in the following sections.

NOTE

Clock configurations change only after POR is asserted.

3.1

Local Bus Mode

Table 13 shows the eight basic clock configurations for the MPC8250. Another 49 configurations are

available by using the configuration pin (RSTCONF) and driving four pins on the data bus.

Table 12. MPC8250 Clocking Modes

Pins

Clocking Mode

PCI Clock

Frequency Range

(MHZ)

Reference

PCI_MODE

PCI_CFG[0] PCI_MODCK 1

Determines PCI clock frequency range. Refer to Section 3.2, “PCI Mode.”

—

Local bus

—

Table 13 and Table 14

PCI host

50–66

Table 15 and Table 16

25–50

PCI agent

50–66

Table 17 and Table 18

25–50

Table 13. Clock Default Configurations

MODCK[1–3]

Input Clock

Frequency

CPM Multiplication

Factor

CPM

Frequency

Core Multiplication

Factor

Core

Frequency

000

33 MHz

100 MHz

133 MHz

001

33 MHz

100 MHz

166 MHz

010

33 MHz

133 MHz

011

33 MHz

133 MHz

166 MHz

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