33689D datasheet(21/31 Pages) FREESCALE

21 / 31 page

Analog Integrated Circuit Device Data

Freescale Semiconductor

33689

FUNCTIONAL DESCRIPTION

FUNCTIONAL INTERNAL BLOCK DESCRIPTION

WINDOW WATCHDOG

The window watchdog can be configured using an external

resistor at WDC pin. The watchdog is cleared through

MODE1 and MODE2 bit in the SPI Register (refer to Table 2,

page 24; also refer to the section entitled Functional Pin

Description on page 19.

A watchdog clear is only allowed in the open window (see

Figure 1). If the watchdog is cleared in the closed window or

has not been cleared at the end of the open window, the

watchdog will generate a reset on the RST pin and reset the

whole device.

Note The watchdog clear in Normal request mode

(150 ms) (first watchdog clear) has no window.

Figure 1. Window Watchdog Operation

Window Watchdog Configuration

If the WDC pin is left open, the default watchdog period is

selected (typ. 150 ms). If no watchdog function is required,

the WDC pin must be connected to GND.

The watchdog timer’s period is calculated using the

following formula:

t WDC = 0.991 * R +0.648 (with R in kΩ and t WDC in ms).

VDD VOLTAGE REGULATOR

The 33689 chip contains a low-power, low dropout voltage

regulator to provide internal power and external power for the

MCU. The on-chip regulator consist of two elements, the

main voltage regulator and the low-voltage reset circuit.

The VDD regulator accepts an unregulated input supply

and provides a regulated VDD supply to all digital sections of

the device. The output of the regulator is also connected to

the VDD pin to provide the 5.0 V to the microcontroller.

Current Limit (Overcurrent) Protection

The voltage regulator has current limit to protect the device

against overcurrent and short circuit conditions.

Overtemperature Protection

The voltage regulator also features overtemperature

protection that has an overtemperature warning (Interrupt -

VDDT) and an overtemperature shutdown.

Stop Mode

During Stop mode, the Stop mode regulator supplies a

regulated output voltage. The Stop mode regulator has a

limited output current capability.

Sleep Mode

In Sleep mode, the voltage regulator external VDD is

turned off.

VDD VOLTAGE REGULATOR TEMPERATURE

PREWARNING

VDD voltage regulator temperature prewarning (VDDT) is

generated if the voltage regulator temperature is above the

TPRE threshold. It will set the VDDT bit in the SPI Register

and an interrupt will be initiated. The VDDT bit remains set as

long as the error condition is present.

During Sleep and Stop modes the VDD voltage regulator

temperature prewarning circuitry is disabled.

HIGH-SIDE SWITCH THERMAL SHUTDOWN

The high-side switch thermal shutdown HSST is

generated if one of the high-side switches HS1:HS3 is above

the HSST threshold. It will shutdown all high-side switches

and set the HSST flag in the SPI Register, and an interrupt

will be initiated. The HSST bit remains set as long as the error

condition is present. During Sleep and Stop modes the high-

side switch thermal shutdown circuitry is disabled.

Window Closed.

Window Open

tWDC * 50%

Watchdog Period

for Watchdog Clear

No Watchdog Clear Allowed

tWDC

33689D датащи(PDF) 21 Page - Freescale Semiconductor, Inc

33689D датащи(HTML) 21 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

датащи скачать

ссылки URL