PLS173 datasheet(5/8 Pages) PHILIPS

5 / 8 page

Philips Semiconductors Programmable Logic Devices

Product specification

PLS173

Programmable logic array

(22

× 42 × 10)

October 22, 1993

AC ELECTRICAL CHARACTERISTICS

°C ≤ Tamb ≤ +75°C, 4.75 ≤ VCC ≤ 5.25V, R1 = 470Ω, R2 = 1kΩ

TEST

LIMITS

SYMBOL

PARAMETER

FROM

CONDITION

MIN

TYP

MAX

UNIT

tPD

Propagation delay2

Input

Output

CL = 30pF

tOE

Output enable1

Input

Output –

CL = 30pF

tOD

Output disable1

Input

Output +

CL = 5pF

NOTES:

1. For 3-State output; output enable times are tested with CL = 30pF to the 1.5V level, and S1 is open for high-impedance to High tests and

closed for high-impedance to Low tests. Output disable times are tested with CL = 5pF. High-to-High impedance tests are made to an output

voltage of VT = (VOH – 0.5V) with S1 open, and Low-to-High impedance tests are made to the VT = (VOL + 0.5V) level with S1 closed.

2. All propagation delays are measured and specified under worst case conditions.

VOLTAGE WAVEFORM

MEASUREMENTS:

All circuit delays are measured at the +1.5V level

of inputs and outputs, unless otherwise specified.

90%

10%

5ns

90%

10%

+3.0V

Input Pulses

TIMING DEFINITIONS

SYMBOL

PARAMETER

tPD

Propagation delay between

input and output.

tOD

Delay between input change

and when output is off (Hi-Z

or High).

tOE

Delay between input change

and when output reflects

specified output level.

TEST LOAD CIRCUIT

TIMING DIAGRAM

+5V

GND

INPUTS

I11

OUTPUTS

DUT

NOTE:

C1 and C2 are to bypass VCC to GND.

VCC

+3V

VOH

VOL

I, B

tPD

1.5V

tOD

tOE

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