PLS153 datasheet(5/9 Pages) PHILIPS

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Philips Semiconductors Programmable Logic Devices

Product specification

PLS153/A

Programmable logic arrays

(18

× 42 × 10)

October 22, 1993

AC ELECTRICAL CHARACTERISTICS

°C ≤ Tamb ≤ +75°C, 4.75V ≤ VCC ≤ 5.25V, R1 = 300Ω, R2 = 390Ω

LIMITS

SYMBOL

PARAMETER

FROM

TEST

PLS153

PLS153A

UNIT

CONDITION

MIN

TYP1

MAX

MIN

TYP1

MAX

tPD

Propagation delay

Input

Output

CL = 30pF

tOE

Output enable2

Input

Output –

CL = 30pF

tOD

Output disable2

Input

Output +

CL = 5pF

NOTES:

1. All typical values are at VCC = 5V, Tamb = +25°C.

2. For 3-State output; output enable times are tested with CL = 30pF to the 1.5V level, and S1 is open for high-impedance to High tests and

closed for high-impedance to Low tests. Output disable times are tested with CL = 5pF. High-to-High impedance tests are made to an output

voltage of VT = (VOH – 0.5V) with S1 open, and Low-to-High impedance tests are made to the VT = (VOL + 0.5V) level with S1 closed.

3. All propagation delays are measured and specified under worst case conditions.

VOLTAGE WAVEFORMS

90%

10%

5ns

90%

10%

+3.0V

MEASUREMENTS:

All circuit delays are measured at the +1.5V level of

inputs and outputs, unless otherwise specified.

Input Pulses

SP00017

TIMING DEFINITIONS

SYMBOL

PARAMETER

tPD

Propagation delay between

input and output.

tOD

Delay between input change

and when output is off (Hi-Z

or High).

tOE

Delay between input change

and when output reflects

specified output level.

TEST LOAD CIRCUIT

+5V

GND

INPUTS

OUTPUTS

DUT

NOTE:

C1 and C2 are to bypass VCC to GND.

VCC

SP00278

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