AD9995 datasheet(13/60 Pages) AD

13 / 60 page

AD9995

–12–

AD9995

–13–

HORIZONTAL CLAMPING AND BLANKING

The AD9995’s horizontal clamping and blanking pulses are fully

programmable to suit a variety of applications. Individual control

is provided for CLPOB, PBLK, and HBLK during the different

regions of each field.This allows the dark pixel clamping and

blanking patterns to be changed at each stage of the readout in

order to accommodate different image transfer timing and high

speed line shifts.

Individual CLPOB and PBLK Patterns

The AFE horizontal timing consists of CLPOB and PBLK, as

shown in Figure 9.These two signals are independently pro-

grammed using the registers in Table III. SPOL is the start

polarity for the signal, and TOG1 and TOG2 are the first and

second toggle positions of the pulse. Both signals are active low

and should be programmed accordingly.

A separate pattern for CLPOB and PBLK may be programmed

for every 10 V-sequences. As described in the Vertical Timing

Generation section, up to 10 separate V-sequences can be created,

each containing a unique pulse pattern for CLPOB and PBLK.

Figure 9 shows how the sequence change positions divide the

readout field into different regions. A different V-sequence can be

assigned to each region, allowing the CLPOB and PBLK signals

to be changed accordingly with each change in the vertical timing.

Individual HBLK Patterns

The HBLK programmable timing shown in Figure 10 is simi-

lar to CLPOB and PBLK. However, there is no start polarity

control. Only the toggle positions are used to designate the start

and stop positions of the blanking period. Additionally, there is a

polarity control HBLKMASK that designates the polarity of the

horizontal clock signals H1–H4 during the blanking period. Set-

ting HBLKMASK high will set H1 = H3 = low and H2 = H4 =

high during the blanking, as shown in Figure 11. As with the

CLPOB and PBLK signals, HBLK registers are available in each

V-sequence, allowing different blanking signals to be used with

different vertical timing sequences.

(3)

(2)

(1)

CLPOB

PBLK

. . .

NOTES

PROGRAMMABLE SETTINGS:

1. START POLARITY (CLAMP AND BLANK REGION ARE ACTIVE LOW)

2. FIRST TOGGLE POSITION

3. SECOND TOGGLE POSITION

ACTIVE

Figure 9. Clamp and Pre-Blank Pulse Placement

Table III. CLPOB and PBLK Pattern Registers

Length

Range

Description

SPOL

High/Low

Starting Polarity of CLPOB/PBLK for V-Sequence 0–9

TOG1

12b

0–4095 Pixel Location

First Toggle Position within Line for V-Sequence 0–9

TOG2

12b

0–4095 Pixel Location

Second Toggle Position within Line for V-Sequence 0–9

Table IV. HBLK Pattern Registers

Length

Range

Description

HBLKMASK

High/Low

Masking Polarity for H1/H3 (0 = H1/H3 Low, 1 = H1/H3 High)

HBLKALT

0–3 Alternation Mode

Enables Odd/Even Alternation of HBLK Toggle Positions 0 =

Disable Alternation. 1 = TOG1–TOG2 Odd,TOG3–TOG6 Even.

2 = 3 = TOG1–TOG2 Even,TOG3–TOG6 Odd

HBLKTOG1

12b

0–4095 Pixel Location

First Toggle Position within Line for Each V-Sequence 0–9

HBLKTOG2

12b

0–4095 Pixel Location

Second Toggle Position within Line for Each V-Sequence 0–9

HBLKTOG3

12b

0–4095 Pixel Location

Third Toggle Position within Line for Each V-Sequence 0–9

HBLKTOG4

12b

0–4095 Pixel Location

Fourth Toggle Position within Line for Each V-Sequence 0–9

HBLKTOG5

12b

0–4095 Pixel Location

Fifth Toggle Position within Line for Each V-Sequence 0–9

HBLKTOG6

12b

0–4095 Pixel Location

Sixth Toggle Position within Line for Each V-Sequence 0–9

REV. 0

AD9995 датащи(PDF) 13 Page - Analog Devices

AD9995 датащи(HTML) 13 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

датащи скачать

ссылки URL