AD9866BCPRL datasheet(21/48 Pages) AD

21 / 48 page

AD9866

Rev. A | Page 21 of 48

Power-Up Default Value

MODE = 0 (Half-Duplex)

MODE = 1 (Full-Duplex)

Address

(Hex) 1

Bit

Break-

down

Description

Width

CONFIG = 0

CONFIG = 1

CONFIG = 0

CONFIG = 1

Comments

(7:5)

CPGA Bias Adjust

(4:3)

SPGA Bias Adjust

0x13

(2:0)

ADC Bias Adjust

0x00

Current bias setting for Rx

path’s functional blocks.

Refer to Page 41.

1 Bits that are undefined should always be assigned a 0.

The AD9866 contains a set of programmable registers described

in Table 10 that are used to optimize its numerous features,

interface options, and performance parameters from its default

been grouped together and assigned adjacent addresses to

minimize the update time when using the multibyte serial port

interface (SPI) read/write feature. Bits that are undefined within

a register should be assigned a 0 when writing to that register.

The default register settings were intended to allow some

applications to operate without the use of an SPI. The AD9866

can be configured to support a half- or full-duplex digital

interface via the MODE pin, with each interface having two

possible default register settings determined by the setting of

the CONFIG pin.

For instance, applications that need to use only the Tx or Rx

path functionality of the AD9866 can configure it for a half-

duplex interface (MODE = 0), and use the TXEN pin to select

between the Tx or Rx signal path with the unused path

remaining in a reduced power state. The CONFIG pin can be

used to select the default interpolation ratio of the Tx path and

RxPGA gain mapping.

SERIAL PORT INTERFACE (SPI)

The serial port of the AD9866 has 3- or 4-wire SPI capability

allowing read/write access to all registers that configure the

device’s internal parameters. Registers pertaining to the SPI are

listed in Table 11. The default 3-wire serial communication port

consists of a clock (SCLK), serial port enable (SEN), and a

bidirectional data (SDIO) signal. SEN is an active low control

gating read and write cycle. When SEN is high, SDO and SDIO

are three-stated. The inputs to SCLK, SEN, and SDIO contain a

Schmitt trigger with a nominal hysteresis of 0.4 V centered

about VDDH/2. The SDO pin remains three-stated in a 3-wire

SPI interface.

Table 11. SPI Registers Pertaining to SPI Options

Address (Hex)

Bit

Description

0x00

(7)

Enable 4-wire SPI

(6)

Enable SPI LSB first

A 4-wire SPI can be enabled by setting the 4-wire SPI bit high,

causing the output data to appear on the SDO pin instead of on

the SDIO pin. The SDIO pin serves as an input-only throughout

the read operation. Note that the SDO pin is active only during

the transmission of data and remains three-stated at any other

time.

An 8-bit instruction header must accompany each read and

write operation. The instruction header is shown in Table 12.

The MSB is an R/Windicator bit with logic high indicating a

read operation. The next two bits, N1 and N0, specify the

number of bytes (one to four bytes) to be transferred during the

data transfer cycle. The remaining five bits specify the address

bits to be accessed during the data transfer portion. The data

bits immediately follow the instruction header for both read

and write operations.

Table 12. Instruction Header Information

MSB

LSB

R/W

The AD9866 serial port can support both MSB (most significant

bit) first and LSB (least significant bit) first data formats. Figure 45

illustrates how the serial port words are built for the MSB first and

LSB first modes. The bit order is controlled by the SPI LSB first bit

(Register 0, Bit 6). The default value is 0, MSB first. Multibyte data

transfers in MSB format can be completed by writing an instruc-

tion byte that includes the register address of the last address to be

accessed. The AD9866 automatically decrements the address for

each successive byte required for the multibyte communication

cycle.

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