SN54HCT645, SN74HCT645

OCTAL BUS TRANSCEIVERS

WITH 3STATE OUTPUTS

SCLS019D − MARCH 1984 − REVISED AUGUST 2003

5

POST OFFICE BOX 655303

PARAMETER MEASUREMENT INFORMATION

From Output

Under Test

RL

VCC

S1

S2

LOAD CIRCUIT

PARAMETER

CL

tPZH

tpd or tt

tdis

ten

tPZL

tPHZ

tPLZ

1 k

Ω

1 k

Ω

50 pF

or

150 pF

50 pF

Open

Closed

RL

S1

Closed

Open

S2

Open

Closed

Closed

Open

50 pF

or

150 pF

Open

Open

−−

NOTES: A. CL includes probe and test-fixture capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.

C. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following

characteristics: PRR

≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns.

D. The outputs are measured one at a time with one input transition per measurement.

E. tPLZ and tPHZ are the same as tdis.

F. tPZL and tPZH are the same as ten.

G. tPLH and tPHL are the same as tpd.

CL

(see Note A)

Test

Point

VOLTAGE WAVEFORM

INPUT RISE AND FALL TIMES

1.3 V

1.3 V

0.3 V

0.3 V

2.7 V

2.7 V

3 V

0 V

tr

tf

Input

VOLTAGE WAVEFORMS

PROPAGATION DELAY AND OUTPUT RISE AND FALL TIMES

1.3 V

1.3 V

1.3 V

10%

10%

90%

90%

3 V

VOH

VOL

0 V

tr

tf

Input

In-Phase

Output

1.3 V

tPLH

tPHL

1.3 V

1.3 V

10%

10%

90%

90%

VOH

VOL

tr

tf

tPHL

tPLH

Out-of-

Phase

Output

1.3 V

10%

90%

3 V

≈VCC

VOL

0 V

Output

Control

(Low-Level

Enabling)

Output

Waveform 1

(See Note B)

1.3 V

tPZL

tPLZ

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES FOR 3-STATE OUTPUTS

VOH

≈0 V

1.3 V

1.3 V

tPZH

tPHZ

Output

Waveform 2

(See Note B)

Figure 1. Load Circuit and Voltage Waveforms