Pin Assignment

SDA

1

10

VIN

SCL

2

SW1

VSEL

SW2

AGND

4

VOUT

CE

5

11: PGND

PGND

The package of GL4010Y4 is DFN2x2-10L, with pin assignment shown in following table:

Pin No

Name

Description

1

SDA

The data signal port of I2C interface

2

SCL

The clock signal port of I2C interface

The pin to choose which voltage setting to be the output voltage.

3

VSEL

There are 2 voltage setting registers inside GL4010Y4, one is

corresponding to VSEL=1 and the other to VSEL=0

4

AGND

The analog ground of the chip. Star connection is recommended for

ground routing to power ground

5

CE

Chip enable pin, pull this pin high to keep the chip working

6, 11

PGND

The power ground of the chip

7

VOUT

The output voltage node, connecting at least 10uF capacitor to power

ground

8

SW2

The output side of switching node

9

SW1

The input side of switching node, connecting the power inductor

between SW1 and SW2

10

VIN

The input power terminal, connecting at least 10uF capacitor to

power ground

3 

9

8

7

6

 

GL4010Y 4

4010