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ADIS16204/PCBZ датащи(PDF) 5 Page - Analog Devices |
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ADIS16204/PCBZ датащи(HTML) 5 Page - Analog Devices |
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5 / 24 page ![]() ADIS16204 Rev. 0 | Page 5 of 24 TIMING SPECIFICATIONS TA = +25°C, VCC = +3.3 V, unless otherwise noted. Table 2. Parameter Description Min1 Typ Max1 Unit fSCLK Fast mode2 0.01 2.5 MHz Normal mode2 0.01 1.0 MHz tDATARATE Chip select period, fast mode2 40 μs Chip select period, normal mode2 100 μs tCSHIGH Chip select high 1/fSCLK tCS Chip select to clock edge 48.8 ns tDAV Data output valid after SCLK edge 100 ns tDSU Data input setup time before SCLK rising edge 24.4 ns tDHD Data input hold time after SCLK rising edge 48.8 ns tDF Data output fall time 5 12.5 ns tDR Data output rise time 5 12.5 ns tSFS CS high after SCLK edge 5 ns 1 Guaranteed by design; typical specifications are not tested or guaranteed. 2 Based on sample rate selection. CS SCLK tDATARATE Figure 2. SPI Chip Select Timing CS SCLK DOUT DIN 12 3 4 5 6 15 16 W/R A5 A4 A3 A2 D2 MSB DB14 D1 LSB DB13 DB12 DB10 DB11 DB2 LSB DB1 tCS tSFS tDAV tDHD tDSU Figure 3. SPI Timing (Utilizing SPI Settings Typically Identified as Phase = 1, Polarity = 1) |
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