ADATE207

Rev. 0 | Page 18 of 36

CONTROL AND STATUS REGISTER INTERFACE

The ADATE207 uses a general-purpose, 16-bit bidirectional,

multiplexed address data bus for computer access of the control

and status registers of the part. All bus activity is registered at

the interface synchronous to the master clock (MCLK), which

is also used by the part for delay timing. Operations the bus

supports include random access reads and writes, as well as

the ability to access blocks of registers in burst.

A description of each register is contained in the Control and

Status Registers section of this document.

READ/WRITE FUNCTION

The control and status register (CSR) bus interface supports the

following functionalities:

•

The ability to enable groups of channels for write

operations, allowing simultaneous programming across all

the designated channels.

•

The ability to select any single channel, or group of

channels, to poll (read) status (where the return value is the

bitwise logical OR of the status returned from each of the

designated channels).

•

The ability to read or write in a single burst operation to a

sequential block of registers significantly reducing the time

required to program the internal memories.

In multiplexing the address and data on the bus, each operation

takes at least two cycles to complete. In all cases, read or write,

the first cycle provides the 16-bit address. This cycle is followed

by one or more data cycles. The quantity of data cycles is

dependent on the activity on the CS_AD and CS_RW_B lines,

which determine the type of operation to perform.

The 16-bit address provided in the first cycle is comprised of

two 5-bit address fields and an additional control field of 6-bits

as shown in Table 12. The control field extends the associated

5-bit register address in use by steering the address and data to

one or more banks of registers within the part.

Register address space consists of five identifiable banks or

groups of register implementations. These include one set of

registers for each of the four channels and a fifth or common

register space. Five bits of addressing are available to all five

address spaces. The bank of registers for each channel duplicates

the other in function and address, allowing a single write

operation to be steered to multiple channels for simultaneous

programming. The fifth bank of registers provides shared

functions, common to all four channels, whose address range is

mapped outside of the register address space used by the

individual channel functions.

All single register, random access operations are performed

with the burst bit of the control field disabled. For these types

of transactions, the 5-bit stop address field is ignored, and the

5-bit start address field is used as the register address of the

operation.

Table 12. Address Bus Decoding

Address Bits

Description

Bit 15

Burst Enable.

1 = initiate burst mode operation.

0 = enable normal read or write transactions.

Bit 14

Common Enable. When set to 1, enables reads or writes to the common registers. This enable is valid in

either normal or burst modes.

Bit 13

Channel 3 Enable. When set to 1, enables reads or writes to Channel 3. This enable is valid in either

normal or burst modes.

Bit 12

Channel 2 Enable. When set to 1, enables reads or writes to Channel 2. This enable is valid in either

normal or burst modes.

Bit 11

Channel 1 Enable. When set to 1, enables reads or writes to Channel 1. This enable is valid in either

normal or burst modes.

Bit 10

Channel 0 Enable. When set to 1, enables reads or writes to Channel 0. This enable is valid in either

normal or burst modes.

Bits[09:05]

Burst Stop Address. Used to set the last CSR address to read to, or write from, before looping back to the

burst start address. This address is only valid when burst enable is set to 1.

Bits[04: 00]

CSR Address (Burst Enable = 0). Used to set the CSR address for reading or writing.

Burst Start Address (Burst Enable = 1). Used to set the first CSR address to read to, or write from, when

bursting data. Burst writes or reads incrementally access successive registers up to, and including, the

burst stop address.