AD9747-EBZ datasheet(7/28 Pages) AD

7 / 28 page

AD9741/AD9743/AD9745/AD9746/AD9747

Rev. 0 | Page 7 of 28

DIGITAL AND TIMING SPECIFICATIONS

TMIN to TMAX, AVDD33 = 3.3 V, DVDD33 = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, IFS = 20 mA, full-scale digital input, maximum

sample rate, unless otherwise noted.

Table 5. AD9741/AD9743/AD9745/AD9746/AD9747

Parameter

Min

Typ

Max

Unit

DAC CLOCK INPUTS (CLKP, CLKN)

Differential Peak-to-Peak Voltage

400

800

1600

Single-Ended Peak-to-Peak Voltage

800

Common-Mode Voltage

300

400

500

Input Current

μA

Input Frequency

250

MHz

DATA CLOCK OUTPUT (DCO)

Output Voltage High

2.4

Output Voltage Low

0.4

Output Current

DAC Clock to Data Clock Output Delay (tDCO)

2.0

2.2

2.8

DATA PORT INPUTS

Input Voltage High

2.0

Input Voltage Low

0.8

Input Current

μA

Data to DAC Clock Setup Time (tDBS Dual-Port Mode)

400

Data to DAC Clock Hold Time (tDBH Dual-Port Mode)

1200

DAC Clock to Analog Output Data Latency (Dual-Port Mode)

Cycles

Data or IQSEL Input to DAC Clock Setup Time (tDBS Single-Port Mode)

400

Data or IQSEL Input to DAC Clock Hold Time (tDBH Single-Port Mode)

1200

DAC Clock to Analog Output Data Latency (Single-Port Mode)

Cycles

SERIAL PERIPHERAL INTERFACE

SCLK Frequency (fSCLK)

MHz

SCLK Pulse Width High (tPWH)

SCLK Pulse Width Low (tPWL)

CSB to SCLK Setup Time (tS)

CSB to SCLK Hold Time (tH)

SDIO to SCLK Setup Time (tDS)

SDIO to SCLK Hold Time (tDH)

SCLK to SDIO/SDO Data Valid Time (tDV)

RESET Pulse Width High

WAKE-UP TIME AND OUTPUT LATENCY

From DAC Outputs Disabled

200

μs

From Full Device Power-Down

1200

μs

DAC Clock to Analog Output Latency (Dual-Port Mode)

Cycles

DAC Clock to Analog Output Latency (Single-Port Mode)

Cycles

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