MPC8323CVRADDC datasheet(15/80 Pages) FREESCALE

15 / 80 page

MPC8323E PowerQUICC™ II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0

Freescale Semiconductor

DDR1 and DDR2 SDRAM

6.2

DDR1 and DDR2 SDRAM AC Electrical Characteristics

This section provides the AC electrical characteristics for the DDR1 and DDR2 SDRAM interface.

6.2.1

DDR1 and DDR2 SDRAM Input AC Timing Specifications

Table 16 provides the input AC timing specifications for the DDR2 SDRAM (Dn_GVDD(typ) = 1.8 V).

Table 17 provides the input AC timing specifications for the DDR1 SDRAM (Dn_GVDD(typ) = 2.5 V).

Table 18 provides the input AC timing specifications for the DDR1 and DDR2 SDRAM interface.

6.2.2

DDR1 and DDR2 SDRAM Output AC Timing Specifications

Table 19 provides the output AC timing specifications for the DDR1 and DDR2 SDRAM interfaces.

Table 16. DDR2 SDRAM Input AC Timing Specifications for 1.8-V Interface

At recommended operating conditions with D

n_GVDD of 1.8 ± 5%.

Parameter

Symbol

Min

Max

Unit

Notes

AC input low voltage

VIL

—

MVREF

nREF – 0.25

AC input high voltage

VIH

MVREF

nREF + 0.25

—

Table 17. DDR1 SDRAM Input AC Timing Specifications for 2.5 V Interface

At recommended operating conditions with D

n_GVDD of 2.5 ± 5%.

Parameter

Symbol

Min

Max

Unit

Notes

AC input low voltage

VIL

—

MVREF

nREF – 0.31

AC input high voltage

VIH

MVREF

nREF + 0.31

—

Table 18. DDR1 and DDR2 SDRAM Input AC Timing Specifications

At recommended operating conditions with D

n_GVDD of (1.8 or 2.5 V) ± 5%.

Parameter

Symbol

Min

Max

Unit

Notes

Controller skew for MDQS—MDQ/MDM

tCISKEW

1, 2

266 MHz

200 MHz

–750

–1250

750

1250

Notes:

1. tCISKEW represents the total amount of skew consumed by the controller between MDQS[n] and any corresponding bit that

will be captured with MDQS[n]. This should be subtracted from the total timing budget.

2. The amount of skew that can be tolerated from MDQS to a corresponding MDQ signal is called tDISKEW. This can be

determined by the following equation: tDISKEW = ±(T/4 – abs(tCISKEW)) where T is the clock period and abs(tCISKEW) is the

absolute value of tCISKEW.

Table 19. DDR1 and DDR2 SDRAM Output AC Timing Specifications

At recommended operating conditions with D

n_GVDD of (1.8 or 2.5 V) ± 5%.

Parameter

Symbol1

Min

Max

Unit

Notes

MCK cycle time, (MCK/MCK crossing)

tMCK

310

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