AM67 datasheet(63/235 Pages) TI1

63 / 235 page

Table 5-29. GPMC0 Signal Descriptions (continued)

SIGNAL NAME [1]

PIN TYPE

[2]

DESCRIPTION [3]

AMW PIN [4]

GPMC0_AD5

GPMC Data 5 Input/Output in A/D non-multiplexed mode

and additionally Address 3 Output in A/D multiplexed

mode

T24

GPMC0_AD6

GPMC Data 6 Input/Output in A/D non-multiplexed mode

and additionally Address 3 Output in A/D multiplexed

mode

T21

GPMC0_AD7

GPMC Data 7 Input/Output in A/D non-multiplexed mode

and additionally Address 3 Output in A/D multiplexed

mode

T22

GPMC0_AD8

GPMC Data 8 Input/Output in A/D non-multiplexed mode

and additionally Address 3 Output in A/D multiplexed

mode

U27

GPMC0_AD9

GPMC Data 9 Input/Output in A/D non-multiplexed mode

and additionally Address 3 Output in A/D multiplexed

mode

U26

GPMC0_AD10

GPMC Data 10 Input/Output in A/D non-multiplexed

mode and additionally Address 11 Output in A/D

multiplexed mode

V27

GPMC0_AD11

GPMC Data 11 Input/Output in A/D non-multiplexed

mode and additionally Address 12 Output in A/D

multiplexed mode

V25

GPMC0_AD12

GPMC Data 12 Input/Output in A/D non-multiplexed

mode and additionally Address 13 Output in A/D

multiplexed mode

V26

GPMC0_AD13

GPMC Data 13 Input/Output in A/D non-multiplexed

mode and additionally Address 14 Output in A/D

multiplexed mode

V24

GPMC0_AD14

GPMC Data 14 Input/Output in A/D non-multiplexed

mode and additionally Address 15 Output in A/D

multiplexed mode

V22

GPMC0_AD15

GPMC Data 15 Input/Output in A/D non-multiplexed

mode and additionally Address 16 Output in A/D

multiplexed mode

V23

GPMC0_BE0n_CLE

GPMC Lower-Byte Enable (active low) or Command

Latch Enable

P27

GPMC0_BE1n

GPMC Upper-Byte Enable (active low)

P26

GPMC0_CSn0

GPMC Chip Select 0 (active low)

R27

GPMC0_CSn1

GPMC Chip Select 1 (active low)

P21

GPMC0_CSn2

GPMC Chip Select 2 (active low)

P22

GPMC0_CSn3

GPMC Chip Select 3 (active low)

P23

GPMC0_WAIT0

GPMC External Indication of Wait

V21

GPMC0_WAIT1

GPMC External Indication of Wait

W26

5.3.13 I2C

5.3.13.1 MAIN Domain

Table 5-30. I2C0 Signal Descriptions

SIGNAL NAME [1]

PIN TYPE

[2]

DESCRIPTION [3]

AMW PIN [4]

I2C0_SCL

IOD

I2C Clock

D23

I2C0_SDA

IOD

I2C Data

B22

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