33874 datasheet(23/37 Pages) FREESCALE

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Analog Integrated Circuit Device Data

Freescale Semiconductor

33874

FUNCTIONAL DEVICE OPERATION

LOGIC COMMANDS AND REGISTERS

A logic [1] on bit D2 (OCL_DIS_s) disables the overcurrent

low detection feature. When disabled, there is no timeout for

the selected output and the overcurrent low detection feature

is disabled.

A logic [1] on bit D3 (OL_DIS_s) disables the open load

(OL) detection feature for the output corresponding to the

state of bits D12:D11.

ADDRESS A1A0100—DIRECT INPUT CONTROL

The DICR register is used by the MCU to enable, disable,

or configure the direct IN pin control of each output. Each

output is independently selected for configuration based on

the state bits D12:D11 (refer to Table 10, page 22).

For the selected output, a logic [0] on bit D1 (DIR_DIS_s)

will enable the output for direct control. A logic [1] on bit D1

will disable the output from direct control.

While addressing this register, if the Input was enabled for

direct control, a logic [1] for the D0 (A/O_s) bit will result in a

Boolean AND of the IN pin with its corresponding IN_SPI

D[4:0] message bit when addressing OCR0. Similarly, a logic

[0] on the D0 pin results in a Boolean OR of the IN pin to the

corresponding message bits when addressing the OCR0.

This register is especially useful if several loads are required

to be independently PWM controlled. For example, the IN

pins of several devices can be configured to operate all of the

outputs with one PWM output from the MCU. If each output

is then configured to be Boolean ANDed to its respective IN

pin, each output can be individually turned OFF by SPI while

controlling all of the outputs, commanded on with the single

PWM output.

A logic [1] on bit D2 (CSNS_high_s) is used to select the

high ratio on the CSNS pin for the selected output. The

default value [0] is used to select the low ratio (Table 14).

A logic [1] on bit D3 (FAST_SR_s) is used to select the

high speed slew rate for the selected output, the default value

[0] corresponds to the low speed slew rate.

ADDRESS 00101—UNDERVOLTAGE/

OVERVOLTAGE AND HS[0,1]

OVERTEMPERATURE REGISTER (UOVR)

The UOVR register disables the undervoltage (D1) and/or

overvoltage (D0) protection. When these two bits are [0], the

under- and overvoltage are active (default value).

The UOVR register allows the overtemperature detection

latching on the HS0 and HS1. To latch the overtemperature,

the bits (OT_latch_1 and OT_latch_0) must be set to [0]

which is the default value. To disable the latching, both bits

must be set to [1].

ADDRESS 01101— WATCHDOG AND HS[2,3]

OVERTEMPERATURE REGISTER (WDR)

The WDR register is used by the MCU to configure the

Watchdog timeout. The Watchdog timeout is configured

using bits D1 and D0. When D1 and D0 bits are programmed

for the desired watchdog timeout period (Table 15), the

WDSPI bit should be toggled as well, ensuring the new

timeout period is programmed at the beginning of a new

count sequence.

The WDR register allows the overtemperature detection

latching on the HS2 and HS3. To latch the overtemperature,

the bits (OT_latch_3 and OT_latch_2) must be set to [0]

which is the default value. To disable the latching, both bits

must be set to [1].

ADDRESS 00110—NO ACTION REGISTER (NAR)

The NAR register can be used to no-operation fill SPI data

packets in a daisy-chain SPI configuration. This would allow

devices to be unaffected by commands being clocked over a

daisy-chained SPI configuration. By toggling the WD bit

(D15) the watchdog circuitry would continue to be reset while

no programming or data read back functions are being

requested from the device.

SERIAL OUTPUT COMMUNICATION (DEVICE

STATUS RETURN DATA)

When the CS pin is pulled low, the output register is

loaded. Meanwhile, the data is clocked out MSB- (OD15-)

first as the new message data is clocked into the SI pin. The

first sixteen bits of data clocking out of the SO, and following

a CS transition, is dependent upon the previously written SPI

word.

Table 14. Current Sense Ratio

CSNS_high_s

* (D2)

Current Sense Ratio

HS0 to HS3

1/7200

1/21400

* “_s” refers to the output, which is selected through bits D12:D11;

refer to Table 10, page 22.

Table 15. Watchdog Timeout

WD[1:0] (D1, D0)

Timing (ms)

558

279

2250

1125

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