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AD5752R датащи(PDF) 6 Page - Analog Devices

номер детали AD5752R
подробное описание детали  Quad 12-Bit Serial Input Unipolar/Bipolar Voltage Output DAC
PDF  20 Pages
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производитель  AD [Analog Devices]
домашняя страница  http://www.analog.com
Logo AD - Analog Devices

AD5752R датащи(HTML) 6 Page - Analog Devices

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AD5726
Rev. 0 | Page 6 of 20
TIMING CHARACTERISTICS
AVDD = +15 V/+5 V, AVSS = −15 V/−5 V/0 V, GND = 0 V; VREFP = +10 V/+2.5 V; VREFN = −10 V/−2.5 V/0 V, VL = 5 V, RLOAD = 2 kΩ,
CL = 200 pF. All specifications TMIN to TMAX, unless otherwise noted.1, 2
Table 5.
Parameter
Limit at TMIN, TMAX
Unit
Description
tDS
5
ns
Data setup time.
tDH
5
ns
Data hold time.
tCH
13
ns
Clock pulse width high.
tCL
13
ns
Clock pulse width low.
tCSS
13
ns
Select time.
tCSH
13
ns
Deselect delay.
tLD1
20
ns
Load disable time.
tLD2
20
ns
Load delay.
tLDW
20
ns
Load pulse width.
tCLRW
20
ns
Clear pulse width.
1 Guaranteed by design and characterization, not production tested.
2 All input control signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
CS
SDIN
SCLK
LDAC
tCSS
tLD1
tCSH
tLD2
A1
A0
X
X
D11
D10
D9
D8
D4
D3
D2
D1
D0
Figure 2. Data Load Sequence
SDIN
SCLK
VOUT
CS
LDAC
tDS
tCL
tCH
tCSH
tLD2
tLDW
tS
tDH
±1LSB
Figure 3. Data Load Timing
CLRSEL
VOUT
CLR
tCLRW
tS
±1LSB
Figure 4. Clear Timing



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