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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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TSL25721 датащи(PDF) 23 Page - OSRAM GmbH |
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TSL25721 датащи(HTML) 23 Page - OSRAM GmbH |
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23 / 41 page  Page 22 Datasheet, Public Document Feedback [v2-00] 2022-Nov-30 TSL2572 − Register O ver view ALS Timing Register (0x01) The ALS timing register controls the internal integration time of the ALS ADCs in 2.73ms increments. Upon power up, the ALS time register is set to 0xFF. Figure 24: ALS Timing Register Wait Time Register (0x03) Wait time is set 2.73 ms increments unless the WLONG bit is asserted in which case the wait times are 12x longer. WTIME is programmed as a 2’s complement number. Upon power up, the wait time register is set to 0xFF. Figure 25: Wait Time Register Note(s): 1. The Wait Time Register should be configured before AEN is asserted. Field Bits Description ATIME 7:0 Value INTEG_CYCLES Time Max Count 0xFF 1 2.73 ms 1024 0xF6 10 27.3 ms 10240 0xDB 37 101 ms 37888 0xC0 64 175 ms 65535 0x00 256 699 ms 65535 Field Bits Description WTIME 7:0 Register Value Wait Time Time (WLONG = 0) Time (WLONG = 1) 0xFF 1 2.73 ms 0.033 s 0xB6 74 202 ms 2.4 s 0x00 256 699 ms 8.4 s |
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