TSL25203 datasheet(53/69 Pages) OSRAM

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[v3-00] 2022-Dec-20

TSL2520 − Register O ver view

VSYNC Period Target Registers

Figure 71:

VSYNC_PERIOD_TARGET

Note(s):

1. Return to the Register Map (0xF4, 0xF5).

VSYNC_CONTROL Register

Figure 72:

VSYNC_CONTROL

Note(s):

1. Return to the Register Map (0xF6).

Addr

Bit

Field

Reset

Type

Description

0xF4

7:0

VSYNC_PERIOD_

TARGET[7:0]

0R/W

VSYNC Period Target

Defines the ideal target value for the VSYNC_PERIOD.

Configure properly before enabling the oscillator

calibration, otherwise it will cause malfunction or

overflow.

See VSYNC_PERIOD_USE_ FAST_TIMING_EVAL for the

calculation of VSYNC_PERIOD_TARGET.

0xF5

6:0

VSYNC_PERIOD_

TARGET[14:8]

0R/W

0xF5

VSYNC_

PERIOD_USE_

FAST_TIMING_

EVAL

0R/W

If set to “0”, the VSYNC_PERIOD_TARGET shall match

VSYNC_PERIOD[15:1], supports range from 15Hz to

500Hz.

VSYNC_PERIOD_TARGET = (720KHz / fVSYNC)/2

e.g. for fVSYNC = 60Hz, VSYNC_PERIOD_TARGET = 0x1770

If set to “1”, the VSYNC_PERIOD_TARGET shall match

VSYNC_PERIOD[14:0], supports range from 30Hz to

1KHz.

VSYNC_PERIOD_TARGET = 720KHz / fVSYNC

e.g. for fVSYNC = 60Hz, VSYNC_PERIOD_TARGET = 0x2EE0

Addr: 0xF6

VSYNC_CONTROL

Bit

Field

Reset

Type

Bit Description

7:2

Reserved

HOLD_VSYNC_PERIOD

R/W

If set to “1” VSYNC_PERIOD[15:8] and VSYNC_

PERIOD[7:0] cannot be updated until VSYNC_

PERIOD[15:8] has been read. It will avoid that

updates during I²C readings.

0SW_VSYNC_TRIGGER

R/W

If VSYNC_MODE is set to “1”, this bit can be used to

trigger a SW sync. In case the exact time is known

between two consecutive I²C reading the offset of

the oscillator frequency can be calculated from the

result in VSYNC_TRIGGER.

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