TMD3702VC datasheet(15/57 Pages) OSRAM

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[v2-00] 2023-Mar-14

TMD3702VC − Detailed Description

I²C Write Transaction

A Write transaction consists of a START, CHIP-ADDRESSWRITE,

byte (9TH clock pulse) the slave places an ACKNOWLEDGE/

NOT-ACKNOWLEDGE (ACK/NACK) on the bus. If NACK is

transmitted by the slave, the master may issue a STOP.

I²C Read Transaction

A Read transaction consists of a START, CHIP-ADDRESSWRITE,

and STOP. Following all but the final byte the master places an

ACK on the bus (9TH clock pulse). Termination of the Read

transaction is indicated by a NACK being placed on the bus by

the master, followed by STOP.

Alternately, if the previous I²C transaction was a Read, the

internal register address buffer is still valid, allowing the

transaction to proceed without “re”-specifying the register

address. In this case the transaction consists of a START,

CHIP-ADDRESSREAD, DATA BYTE(S), and STOP. Following all but

the final byte the master places an ACK on the bus (9TH clock

pulse). Termination of the Read transaction is indicated by a

NACK being placed on the bus by the master, followed by STOP.

The I²C bus protocol was developed by Philips (now NXP). For

a complete description of the I²C protocol, please review the

NXP I²C design specification at:

www.i2c-bus.org/references/

Figure 18:

I²C Timing Diagrams

START

STOP

tBUF

tLOW

tHD; STA

VIH

VIL

VIH

VIL

tSU; DAT

tSU; STA

tHD; DAT

tHIGH

tSU; STO

SCL

SDA

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