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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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LM1771SMM датащи(PDF) 14 Page - National Semiconductor (TI) |
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LM1771SMM датащи(HTML) 14 Page - National Semiconductor (TI) |
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14 / 17 page  Layout The LM1771, like all switching regulators, requires careful attention to layout to ensure optimal performance. The fol- lowing steps should be taken to aid in the layout. For more information refer to Application Note AN-1299. 1. Ensure that the ground connections of the input capaci- tor, output capacitor and NMOS are as close as pos- sible. Ideally these should all be grounded together in close proximity on the component side of the board. 2. Keep the switch node small to minimize EMI without degrading thermal cooling of the FETs. 3. Locate the feedback resistors close to the IC and keep the feedback trace as short as possible. Do not run any feedback traces near the switch node. 4. Keep the gate traces short and keep them away from the switch node as much as possible. 5. If a small bypass capacitor is used on V IN (0.1µF) place it as close to the pin, with the ground connection as close to the chip ground as possible. www.national.com 14 |
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