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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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ADS6445 датащи(PDF) 57 Page - STMicroelectronics |
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ADS6445 датащи(HTML) 57 Page - STMicroelectronics |
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57 / 75 page  www.ti.com D13 (D0) 0 (D0) D1 (0) 0 (D0) 0 (D1) D0 (0) 0 (D1) D13 (D2) D12 (D3) D11 (D4) D10 (D5) D9 (D6) D7 (D8) D8 (D7) D6 (D9) D5 (D10) D4 (D11) D3 (D12) D2 (D13) D13 (D2) D6 (D7) D10 (D3) D3 (D10) D7 (D6) D0 (D13) D12 (D1) D12 (D1) D5 (D8) D9 (D4) D2 (D11) D11 (D2) D4 (D9) D8 (D5) D1 (D12) D13 (D0) DataBitinLSBFirstMode DataBitinMSBFirstMode (1) In16-Bitserialization,twozerobitsarepaddedtothe14-bit ADCdataontheMSBside. OutputData DA,DB,DC,DD DataRate=16 Fs ´ InputClock, CLKP/M Freq=Fs FrameClock, FCLKP Freq=1 Fs ´ BitClock – DDR, DCLKP/M Freq=8 Fs ´ T0225-02 OutputData DA,DB,DC,DD DataRate=14 Fs ´ BitClock – DDR, DCLKP/M Freq=7 Fs ´ SampleN SampleN+1 2-WIRE INTERFACE - 16 × SERIALIZATION WITH DDR/SDR BIT CLOCK ADS6445, ADS6444 ADS6443, ADS6442 SLAS531 – MAY 2007 Figure 93. 1-Wire Interface The 2-wire interface is recommended for sampling frequencies above 65 MSPS. In 16 × serialization, two zero bits are padded to the 14-bit ADC data on the MSB side and the combined 16-bit data is serialized and output over two LVDS pairs. The data rate is 8 × Sample frequency since 8 bits are sent on each wire every clock cycle. The data is available along with DDR bit clock or optionally with SDR bit clock. Each ADC sample is sent over the 2 wires as byte-wise or bit-wise or word-wise. Using the 16 × serialization makes it possible to upgrade to a 16-bit ADC in the future seamlessly, without requiring any modification to the receiver capture logic design. 57 Submit Documentation Feedback |
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