Philips Semiconductors

Product specification

PCK2509SA

50–150 MHz 1:9 SDRAM clock driver

2000 Dec 01

4

FUNCTIONAL BLOCK DIAGRAM

FBOUT

FBIN

CLK

1G

11

24

13

23

PLL

2Y3

2Y2

2Y1

2Y0

1Y4

1Y3

1Y2

1Y1

1Y0

3

4

5

8

9

21

20

17

16

12

SW00388

2G

14

The PLL clock distribution device and A[L]VC registered drivers reduce

signal loads on the memory controller and prevent timing delays and

waveform distortions that would cause unreliable operation

A[L]VC

PCK2509SA

A[L]VC

FRONT SIDE

A[L]VC

SW00431