ACT86600 datasheet(54/56 Pages) QORVO

54 / 56 page

ACT86600

Hybrid PMIC for Enterprise

Storage and Computing

Data Sheet Rev. B, February 2, 2023

Subject to change without notice

54 of 56

www.qorvo.com

excessive EMI on the feedback paths and voltage

gradients in the ground plane, both of which can result

in instability or regulation errors. Follow these layout

guidelines when designing the ACT86600 PCB. Refer

to the Qorvo ACT86600 Evaluation Kit for a layout

example.

Place the AVIN input capacitors as close as

possible to the IC. Connect the capacitors

directly to the AVIN input pin and PGND power

ground pin. Do not use vias to route power

between the input capacitors and the IC.

Minimize the switch node trace length between

SW7 and the inductor. Avoid routing sensitive

analog signals near these high frequency, high

dV/dt traces.

The input capacitor and output capacitor

grounds should be connected as close together

as possible, with short, direct, and wide traces.

Connect the PGND ground pin and the AGND

ground pin directly to the exposed pad under

the IC. The AGND ground plane should be

routed separately from the other ground planes

and only connect to the main ground plane

under the IC at the AGND pin.

Connect a 10µF capacitor directly to the VCC5

pin and AGND as close to the IC as possible to

minimize noise on VCC5 because it provides

power to sensitive analog internal circuitry.

Then route the VCC5 net directly to the output

capacitor. Do not connect VCC5 to the output

power plane at the inductor.

Connect the exposed pad directly the top layer

ground plane. Connect the top layer ground

plane to both internal ground planes and the

PCB backside ground plane with thermal vias.

Provide ground plane routing on multiple layers

that allows the IC’s heat to flow into the PCB

and then spread radially from the IC. Avoid

cutting the ground planes and adding vias that

restrict the radial flow of heat of operating

conditions.

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