PCK2057 datasheet(8/12 Pages) PHILIPS

8 / 12 page

Philips Semiconductors

Product data

PCK2057

70 – 190 MHz I2C differential 1:10 clock driver

2001 Jun 12

AC CHARACTERISTICS

SYMBOL

PARAMETER

TEST CONDITIONS

LIMITS

UNIT

SYMBOL

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

tPD

Propagation delay time

Test mode/CLK to any output

—

3.7

—

tPHL

HIGH-to-LOW level propagation delay time

SCL to SDA (acknowledge)

—

500 1

—

ten

Output enable time

Test mode/SDA to Y output

—

tdis

Output disable time

Test mode/SDA to Y output

—

tjit(per)

Jitter (period); see Figure 4

100 MHz to 167 MHz

–75

—

tjit(cc)

Jitter (cycle-to-cycle); see Figure 5

100 MHz to 167 MHz

–75

—

tjit(hper)

Half-period jitter; see Figure 6

100 MHz to 167 MHz

–90

—

t∅

Static phase offset; see Figure 1

133 MHz/VID on CLK = 0.71 V

220

—

450

t∅

Static phase offset; see Figure 1

167 MHz/VID on CLK = 0.71 V

140

—

270

tslr(o)

Output clock slew rate; see Figure 3

terminated with 120

Ω/14 pF

—

V/ns

tsk(o)

Output skew; see Figure 2

—

SSC modulation frequency

—

33.3

kHz

SSC clock input frequency deviation

0.00

—

–0.50

NOTE:

1. This time is for a PLL frequency of 100 MHz.

AC WAVEFORMS

SW00882

t(O) = Σ

n =N

t(O)n

t(O)n + 1

(N is a large number of samples)

CLK

FBIN

Figure 1. Static phase offset

SW00883

tsk(O)

Yx, FBOUT

Figure 2. Output skew

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