Philips Semiconductors

Product specification

PCK2014A

CK98 (100/133 MHz) spread spectrum

system clock generator

2001 Apr 02

8

AC CHARACTERISTICS

CPU CLOCK OUTPUTS, CPU(0–5) (LUMP CAPACITANCE TEST LOAD = 20 pF)

SYMBOL

PARAMETER

LIMITS

LIMITS

UNIT

NOTES

SYMBOL

PARAMETER

133 MHz MODE

100 MHz MODE

UNIT

NOTES

MIN

MAX

MIN

MAX

Average CPUCLK period

7.5

7.65

10.0

10.3

ns

2, 9

Absolute minimum CPUCLK period

7.35

n/a

9.85

n/a

ps

CPUCLK HIGH time

1.87

n/a

3.0

n/a

ns

5, 10

CPUCLK LOW time

1.67

n/a

2.8

n/a

ns

6, 10

CPUCLK rise time

0.4

1.6

0.4

1.6

ns

8

CPUCLK fall time

0.4

1.6

0.4

1.6

ns

8

CPUCLK cycle-cycle jitter

150

150

ps

DUTY CYCLE

Output Duty Cycle

45

55

45

55

%

1

CPUCLK pin-pin skew

175

175

ps

2

PCI CLOCK OUTPUTS, PCI(0–5) (LUMP CAPACITANCE TEST LOAD = 30 pF)

SYMBOL

PARAMETER

LIMITS

LIMITS

UNIT

NOTES

SYMBOL

PARAMETER

133 MHz MODE

100 MHz MODE

UNIT

NOTES

MIN

MAX

MIN

MAX

PCI period

30.0

n/a

30.0

n/a

ns

2, 9

PCI HIGH time

12.0

n/a

12.0

n/a

ns

5, 10

PCI LOW time

12.0

n/a

12.0

n/a

ns

6, 10

PCI rise time

0.5

2.0

0.5

2.0

ns

8

PCI fall time

0.5

2.0

0.5

2.0

ns

8

PCI cycle-cycle jitter

300

300

ps

DUTY CYCLE

PCI Duty Cycle

45

55

45

55

%

1

PCI pin-pin skew

500

500

ps

2

APIC(0–1) CLOCK OUTPUT (LUMP CAPACITANCE TEST LOAD = 20 pF)

SYMBOL

PARAMETER

LIMITS

LIMITS

UNIT

NOTES

SYMBOL

PARAMETER

133 MHz MODE

100 MHz MODE

UNIT

NOTES

MIN

MAX

MIN

MAX

APIC CLK period

60.0

61.2

60.0

61.2

ns

2, 9

APIC CLK HIGH time

25.5

n/a

25.5

n/a

ns

5, 10

APIC CLK LOW time

25.3

n/a

25.3

n/a

ns

6, 10

APIC CLK rise time

0.4

1.6

0.4

1.6

ns

8

APIC CLK fall time

0.4

1.6

0.4

1.6

ns

8

APIC CLK cycle-cycle jitter

500

500

ps

DUTY CYCLE

APIC CLK Duty Cycle

45

55

45

55

%

1

APIC CLK pin-pin skew

250

250

ps

2