PCF8801 datasheet(8/20 Pages) PHILIPS

8 / 20 page

2000 Feb 04

Philips Semiconductors

Product speciﬁcation

LCD driver for 140

× 2 segments

PCF8801

Internal oscillator

The internal oscillator generates two identical LCD

multiplexing clock signals (INT_OSCO) having a minimum

frequency of 240 Hz at pads INT_OSCO1 and

INT_OSCO2. The internal oscillator is enabled by

connecting an external resistor between pad REXT

and VDD, and disabled (INT_OSCO = 0) by connecting

pad REXT to VSS. An external resistor value of 330 kΩ will

typically generate a frequency of 500 Hz.

For cascade applications, the first chip in the cascade

should have pad INT_OSCO connected to pad OSCI.

Each OSCI pad of all subsequent chips should be

connected to the OSCO pad of the previous chip (see

Fig.4). The signal applied to the OSCI pad must always be

a clock signal; applying a DC signal could damage the

LCD.

Power-on reset and external reset

At power-on, the PCF8801 resets to the following

conditions:

• The shift register and the output register sets all bits to 0

• The frame generator outputs (COMMON and M) are 0

• The multiplexed outputs (S1 to S140) to the LCD pixels

are 0

• The backplane driver outputs (COM1 and COM2) are 0

until the first falling edge of OSCI (see Fig.2).

A positive pulse on pad RESET (active HIGH) has the

same effect as the power-on reset. A HIGH-level on

pad RESET disables all clock inputs, the bias generator,

and the internal oscillator (INT_OSCO = 0). If the RESET

input is not used, it is advisable to connect its pad directly

to the adjacent pad VSS5. However, if the RESET input is

to be used in a chip-on-glass application, it is strongly

advised that the RESET input is connected in series with

an on-glass resistance to reduce its sensitivity to

ESD/EMC disturbances. The minimum value of resistance

recommended by the ITO is 8 k

Ω.

Cascading

To reduce the length of routing required between

cascaded chips on-glass, all inputs/outputs for control

lines, clock signals and data are provided at both sides of

the narrow package. An example of cascading is shown in

Fig.4.

handbook, full pagewidth

DIR

DATA IN

REXT

Rext

330 k

Ω

VDD

VSS

CLKI

CLKO

LDPO

LDNO

OSCO

CLOCK

LDPI

LOAD

LDNI

VDD

VSS

OSCI

INT_OSCO

RESET

PCF8801

chip 1

chip 2

DIR

REXT

VSS

CLKI

CLKO

LDPO

LDNO

OSCO

LDPI

LDNI

VDD

OSCI

INT_OSCO

RESET

MGL918

Fig.4 Example of cascading.

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