6

AT93C46

5140B–SEEPR–2/07

ERASE ALL (ERAL): The Erase All (ERAL) instruction programs every bit in the mem-

ory array to the logic “1” state and is primarily used for testing purposes. The DO pin

outputs the Ready/Busy status of the part if CS is brought high after being kept low for a

WRITE ALL (WRAL): The Write All (WRAL) instruction programs all memory locations

with the data patterns specified in the instruction. The DO pin outputs the Ready/Busy

ERASE/WRITE DISABLE (EWDS): To protect against accidental data disturb, the

Erase/Write Disable (EWDS) instruction disables all programming modes and should be

executed after all programming operations. The operation of the Read instruction is

independent of both the EWEN and EWDS instructions and can be executed at any

time.

Timing Diagrams

Figure 2. Synchronous Data Timing

Note:

1. This is the minimum SK period.

µs

Table 6. Organization Key for Timing Diagrams

I/O

AT93C46 (1K)

x 8

x 16