PCF8566P datasheet(14/40 Pages) PHILIPS

14 / 40 page

1998 May 04

Philips Semiconductors

Product speciﬁcation

Universal LCD driver for low multiplex

rates

PCF8566

There is a one-to-one correspondence between the RAM

addresses and the segment outputs, and between the

individual bits of a RAM word and the backplane outputs.

The first RAM column corresponds to the 24 segments

operated with respect to backplane BP0 (see Fig.9).

In multiplexed LCD applications the segment data of the

second, third and fourth column of the display RAM are

time-multiplexed with BP1, BP2 and BP3 respectively.

When display data are transmitted to the PCF8566 the

display bytes received are stored in the display RAM

according to the selected LCD drive mode. To illustrate the

filling order, an example of a 7-segment numeric display

showing all drive modes is given in Fig.10; the RAM filling

organization depicted applies equally to other LCD types.

With reference to Fig.10, in the static drive mode the eight

transmitted data bits are placed in bit 0 of eight successive

display RAM addresses. In the 1 : 2 multiplex drive mode

the eight transmitted data bits are placed in bits 0 and 1 of

four successive display RAM addresses. In the 1 : 3

multiplex drive mode these bits are placed in

bits 0, 1 and 2 of three successive addresses, with bit 2 of

the third address left unchanged. This last bit may, if

necessary, be controlled by an additional transfer to this

address but care should be taken to avoid overriding

adjacent data because full bytes are always transmitted.

In the 1 : 4 multiplex drive mode the eight transmitted data

bits are placed in bits 0, 1, 2 and 3 of two successive

display RAM addresses.

6.14

Data pointer

The addressing mechanism for the display RAM is

realized using the data pointer. This allows the loading of

an individual display data byte, or a series of display data

bytes, into any location of the display RAM.

The sequence commences with the initialization of the

data pointer by the LOAD DATA POINTER command.

Following this, an arriving data byte is stored starting at the

display RAM address indicated by the data pointer thereby

observing the filling order shown in Fig.10. The data

pointer is automatically incremented according to the LCD

configuration chosen. That is, after each byte is stored, the

contents of the data pointer are incremented by eight

(static drive mode), by four (1 : 2 multiplex drive mode), by

three (1 : 3 multiplex drive mode) or by two (1 : 4 multiplex

drive mode).

6.15

Subaddress counter

The storage of display data is conditioned by the contents

of the subaddress counter. Storage is allowed to take

place only when the contents of the subaddress counter

agree with the hardware subaddress applied to

A0, A1 and A2 (pins 7, 8, and 9). A0, A1 and A2 should

be tied to VSS or VDD. The subaddress counter value is

defined by the DEVICE SELECT command. If the contents

of the subaddress counter and the hardware subaddress

do not agree then data storage is inhibited but the data

pointer is incremented as if data storage had taken place.

The subaddress counter is also incremented when the

data pointer overflows.

The storage arrangements described lead to extremely

efficient data loading in cascaded applications. When a

series of display bytes are being sent to the display RAM,

automatic wrap-over to the next PCF8566 occurs when

the last RAM address is exceeded. Subaddressing across

device boundaries is successful even if the change to the

next device in the cascade occurs within a transmitted

character.

Fig.9

Display RAM bit-map showing direct relationship between display RAM addresses and segment outputs,

and between bits in a RAM word and backplane outputs.

handbook, full pagewidth

1234

display RAM addresses (rows)/segment outputs (S)

display RAM bits

(columns) /

backplane outputs

(BP)

MGG389

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