PCF8558USLASH12 datasheet(10/24 Pages) PHILIPS

10 / 24 page

1998 Apr 07

Philips Semiconductors

Objective speciﬁcation

Universal LCD driver for small graphic

panels

PCF8558

COMMANDS

Display Control

Table 2

Display status

PD: POWER-DOWN

• All LCD outputs at VDD (display off)

• Bias generator off

• Power-on reset on, oscillator off (external clock still

possible)

• VLCD can be disconnected

• I2C-bus, RAM, commands, etc. still function in

power-down mode.

Set Address

Table 3

Y0, Y1 and Y2 define the Y address vector

address of the display RAM

BIT

LOGIC 0

LOGIC 1

normal

power-down

horizontal addressing

vertical addressing

DISPLAY STATUS

BITS

Blank

Normal

All segments on

Inverse video

LINE

0000

0011

0102

0113

1004

Set X address

The X address points to the columns. The range of X is

0 to 100 (64H).

Reset function

After power-on the chip has the following state:

• Power-down mode (PD = 1)

• RAM undefined

• RAM X and Y address undefined

• Display control bits (except PD) undefined

• I2C-bus interface reset.

Note

If the chip is used with an external clock source, after

power-on, the chip requires at least 2 clock pulses to

ensure that an internal synchronous reset is carried out.

After the internal reset, the chip goes into power-down

mode (PD = 1). If the clock pulses are not supplied, and

the reset is not cleared, the chip cannot respond to

commands in the I2C bus.

In applications where the internal oscillator is used

(pin OSC = VDD), the oscillator starts after power-on.

As soon as the synchronous reset is cleared, the chip goes

into power-down mode, and the oscillator is stopped.

Table 4

Instructions: control byte, address

INSTRUCTION

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

DESCRIPTION

Display control

Y address vector, display control

X address

set column address

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