PCF8558 datasheet(15/24 Pages) PHILIPS

15 / 24 page

1998 Apr 07

Philips Semiconductors

Objective speciﬁcation

Universal LCD driver for small graphic

panels

PCF8558

AC CHARACTERISTICS

All timing values are referenced to VIH and VIL levels with an input voltage swing of VSS to VDD. VDD = 2.5 to 6 V;

VSS =0V;VLCD =VDD − 3.5VtoVDD − 9V;Tamb = −40 to +85 °C; unless otherwise speciﬁed.

Notes

1. The rise and fall times specified here refer to the driver device (i.e. not PCF8558) and are part of the general fast

I2C-bus specification. However, when PCF8558 asserts an acknowledge on SDA, the fall time is given by parameter

tf. Cb = capacitive load per bus line.

2. The device inputs SDA and SCL are filtered and will reject spikes on the bus lines of width <tSW(max).

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

fFR)

LCD frame frequency

(internal oscillator)

62.5

fOSC(ext)

external clock frequency

150

225

kHz

tPLCD

driver delays

VDD − VLCD =9V;

with test loads

−−

100

µs

I2C-bus (see Fig.12)

fSCL

SCL clock frequency

−−

400

kHz

tCLKL

SCL LOW time

1.3

−−µs

tCLKH

SCL HIGH time

0.6

−−µs

tBUF

bus free time

between successive STOP

and START conditions

1.3

−−µs

SCL and SDA rise time

note 1

−−

300

SCL and SDA fall time

note 1

20 + 0.1Cb

−

300

tSU;STA

START condition set-up time

repeated start codes only

0.6

−−µs

tHD;STA

START condition hold time

0.6

−−µs

tSU;DAT

data set-up time

100

−−

tHD;DAT

data hold time

−−

tSU;STO

STOP condition set-up time

0.6

−−µs

tSW

tolerable spike width on bus

note 2

−−

capacitive load per bus line

−−

400

Fig.11 AC test loads.

handbook, full pagewidth

MGG564

1.5 k

Ω

VDD

SDA

1 nF

R1 to R40,

C1 to C101

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